Renesas Hitachi H8S/2191, Hardware Manual

Page: 133 / 1065

Rev. 2.0, 11/00, page 106 of 1037
6.3 Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts.
6.3.1 External Interrupts
There are seven external interrupt sources; NMI and IRQ5 to IRQ0. Of these, NMI, and IRQ1 to
IRQ0 can be used to restore this chip from standby mode.
(1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the
interrupt control mode and the status of the CPU interrupt mask bits. The NMIEG1 and
NMIEG0 bits in SYSCR can be used to select whether an interrupt is requested at a rising,
falling edge or both edges on the
10, pin.
The vector number for NMI interrupt exception handling is 7.
(2) IRQ5 to IRQ0 Interrupts
Interrupts IRQ5 to IRQ0 are requested by an input signal at pins
,54 to ,54. Interrupts
IRQ5 to IRQ0 have the following features:
(a) Using IEGR, it is possible to select whether an interrupt is generated by a low level,
falling edge, rising edge, or both edges, at pin
,54.
(b) Using IEGR, it is possible to select whether an interrupt is generated by a low level,
falling edge, rising edge, or both edges, at pins
,54 to ,54.
(c) Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IENR.
(d) The interrupt control level can be set with ICR.
(e) The status of interrupt requests IRQ5 to IRQ0 is indicated in IRQR. IRQR flags can be
cleared to 0 by software.
A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 6.2.
Clear signal
R
S
Q
Edge detection
circuit
IRQnEG IRQnF
IRQnE
Note: n = 5 to 0
IRQn interrupt
request
IRQn input
Figure 6.2 Block Diagram of Interrupts IRQ5 to IRQ0