Renesas Hitachi H8S/2191, Hardware Manual, Page: 386 / 1065

Rev. 2.0, 11/00, page 359 of 1037
17.2 Descriptions of Respective Registers
17.2.1 Free Running Counter (FRC)
Free running counter H (FRCH)
Free running counter L (FRCL)
0
3
0
R/W
5
0
R/W
7
0
9
0
R/W
11
0
13
0
15
R/W R/W R/W
0
R/W R/W
1
0
2
0
R/W
4
0
R/W
6
0
8
0
R/W
10
0
12
0
14
FRC
FRCH FRCL
R/W R/W R/W R/W
0
R/W
0
Bit :
Initial value :
R/W :
The FRC is a 16-bit read/write up-counter which counts up by the inputting internal
clock/external clock. The inputting clock is to be selected from the CKS1 and CKS0 of the
TCRX.
By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A.
When the FRC overflows (H'FFFF
→
H'0000), the OVF of the TCSRX will be set to 1.
At this time, when the OVIE of the TIER is being set to 1, an interrupt request will be issued to
the CPU.
Reading/writing can be made from and to the FRC through the CPU at 8-bit or 16-bit.
The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.