Renesas Hitachi H8S/2191, Hardware Manual

Page: 695 / 1065

Rev. 2.0, 11/00, page 668 of 1037
(10) FIFO Timer Capture Register (FTCTR)
0
R
13
0
R
14
0
R
15 1 0 3 2 5 4 7
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R R R R R R R
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0
FTCTR is a register to display the count of the 16-bit timer counter.
FTCTR is a 16-bit read-only register. It stores the counter value if a VD signal was detected in
PB mode. Only a word access is accepted. If a byte access is attempted, resulting operation is
not assured. It is initialized to H'0000 by a reset or stand-by.
Note: Its address is shared with the FIFO timing pattern register 1 (FTPRA). Accordingly, if a
write is attempted, the value is written in FTPRA.
(11) DFG Reference Count Register (DFCTR)
0
0
1
0
R
2
0
R
3
0
4
0
R
5 6
1
7
— — —
— — —
DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
R R
1 1
Bit :
Initial value :
R/W :
DFCTR is a register to count the DFG pulses.
DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved. If a read is attempted, 1 is read
out. It is initialized to H'E0 by a reset or stand-by.
Note: Its address is shared with the DFG reference register 1 (DFCRA). Accordingly, if a
write is attempted, the value is written in DFCRA.
Bits 4 to 0: DFG Pulse Count Bits (DFCTR4 to DFCTR0)
Count the number of pulses of DFG.