Renesas Hitachi H8S/2191, Hardware Manual

Page: 731 / 1065

Rev. 2.0, 11/00, page 704 of 1037
28.8.4 Register Descriptions
(1) CFG Speed Preset Data Register (CFPR)
0
W
13
0
W
14
0
W
15 1 0 3 2 5 4 7
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W W W W W W W
12
0 0 0 0 0 0
Bit :
Initial value :
R/W :
The 16-bit preset data that defines the specified CFG speed is set in CFPR. The preset data is
referenced to H'8000*, and can be calculated from the following equation.
φ
s/n
CFG speed preset data =H'8000
−
(
−
2)
DVCFG frequency
φ
s: Servo clock frequency in Hz (f
OSC
/2)
DVCFG frequency: In Hz
The constant 2 is the preset interval (see figure 28.33).
φ
s/n: Clock source of the selected counter
CFPR is a 16-bit write-only register. CFPR is accessible by word access only. Byte access
gives unassured results. No read is valid. If a read is attempted, an undetermined value is read
out. CFPR is initialized to H'0000 by a reset, stand-by or module stop.
Note: * The preset data value is calculated so that the counter will reach H'8000 when the
error is zero. When the counter value is latched as error data in the CFG speed error
data register (CFER), however, it is converted to a value referenced to H'0000.