Renesas Hitachi H8S/2191, Hardware Manual, Page: 523 / 1065

Rev. 2.0, 11/00, page 496 of 1037
Between serial transmission initialization and setting of the TE bit to 1, the mark state is
replaced by the value of PDR (the pin does not function as the SO1 pin until the TE bit is set
to 1). Consequently, PCR and PDR for the port corresponding to the SO1 pin should first be
set to 1.
To send a break during serial transmission, first clear PDR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the SO1 pin becomes an I/O port, and 0 is output from the SO1 pin.
(5) Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1,
even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
(6) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI1 operates on a base clock with a frequency of 16 times the
transfer rate.
In reception, the SCI1 samples the falling edge of the start bit using the base clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the base clock. This is illustrated in figure 23.21.
Internal
base clock
16 clocks
8 clocks
Receive data
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 0 0 7
Figure 23.21 Receive Data Sampling Timing in Asynchronous Mode