Renesas Hitachi H8S/2191, Hardware Manual, Page: 995 / 1065

Rev. 2.0, 11/00, page 968 of 1037
H'D119: Timer R Mode Register TMRM2: Timer R
0
0
1
0
R/(W)
*
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/(W)
*
R/W R/W
PS10
R/W
PS11
0
R/W
LAT PS31 PS30 CP/SLM CAPF SLW
TMRU-1 clock source select bits
TMRU-1 clock source select
0 0 Count at CFG rising edge
PS10 PS11
1 PSS, count at
φ
/4
0 1 PSS, count at
φ
/256
1 PSS, count at
φ
/512
TMRU-3 clock source select bits
TMRU-3 clock source select
0 0 Count at rising edge of DVCTL from frequency divider
PS30 PS31
1 PSS, count at
φ
/4096
0 1 PSS, count at
φ
/2048
1 PSS, count at
φ
/1024
Interrupt select bit
Interrupt request by TMRU-2 capture signal is enabled
Interrupt request by slow tracking mono-multi end is enabled
0
1
Capture signal flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMRU-2 capture signal is generated while CP/SLM bit = 0
0
1
Slow tracking mono-multi flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When slow tracking mono-multi ends while
CP/SLM bit = 1
0
1
TMRU-2 captrue signal select bits
*
0 Capture at TMRU-3 underflow
CPS LAT
0 1 Capture at CFG rising edge
1 Capture at IRQ3 edge
TMRU-2 capture signal select
Note:
*
Don't care.
Bit :
Initial value :
R/W :
Note:
*
Only 0 can be written to clear the flag.