Renesas Hitachi H8S/2191, Hardware Manual, Page: 840 / 1065

Rev. 2.0, 11/00, page 813 of 1037
(2) Servo Interrupt Permission Register 2 (SIENR2)
0
0
1
0
R/W
2 3 4 5 6
1
7
— — — — — —
— — — — — —
R/W
IESNC IECTL
1 1 1 1 1
Bit :
Initial value :
R/W :
SIENR2 controls the permission and prohibition of the interrupt of the servo section. SIENR2 is
an 8-bit readable/writable register. It is initialized to H'FC by a reset, stand-by or module stop.
Bits 7 to 2: Reserved
No read or write is valid. If a read is attempted, an undetermined value is read out.
Bit 1: Vertical Sync Signal Interrupt Permission Bit (IESNC)
Bit 1
IESNC Description
0 Prohibits the interrupt (interrupt to the vertical sync signal) request through IRRSNC
(Initial value)
1 Permits the interrupt request through IRRSNC
Bit 0: CTL Interrupt Permission Bit (IECTL)
Bit 0
IECTL Description
0 Prohibits the interrupt request through IRRCTL (Initial value)
1 Permits the interrupt request through IRRCTL