Renesas Hitachi H8S/2191, Hardware Manual

Page: 626 / 1065

Rev. 2.0, 11/00, page 599 of 1037
(3) When condition is not satisfied by Bcc instruction (16-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not
satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address
trap interrupt after executing the trap address instruction (if the trap address instruction is
that of 2 states or more. If the instruction is that of 1 state, after executing two instructions).
The address to be stacked is 02C0.
Address bus
Interrupt
request
signal
Start of
exception handling
02B8 02C0 02BC 02BE 02C2 02BA
02B8 BEQ NEXT:16
02BC NOP
02BE NOP
02C0 NOP
02C2 NOP
02C4 NOP
(NEXT = H'02C4)
*
BEQ
execution
NOP
execu-
tion NOP
execu-
tion
Data
fetch Internal
opera-
tion
* Trap setting address
The underlines address is the
one to be actually stacked.
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NEXT:
Figure 27.8 When the Condition is Not Satisfied by Bcc Instruction (16-bit Displacement)