Renesas Hitachi H8S/2191, Hardware Manual

Page: 742 / 1065

Rev. 2.0, 11/00, page 715 of 1037
(3) Capstan Phase Error Detection Control Register (CPGCR)
0
1
1 2
— — —
— — —
1
3
0
4
0
R/W
5
0
6
0
7
R/W R/(W)
*
CPOVF
R/W
CPCS0
0
R/W
CPCS1 CR/RF SELCFG2
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
CPGCR controls the operation of capstan phase error detection.
CPGCR is an 8-bit readable/writable register. Bits 2 to 0 are reserved, bit 5 accepts only read
and 0 write.
It is initialized to H'07 by a reset or stand-by.
Bits 7 and 6: Clock Source Selection Bits (CPCS1, CPCS0)
Select the clock supplied to the counter. (
φ
s = fosc/2)
Bit 7 Bit 6
CPCS1 CPCS0 Description
0
φ
s (Initial value) 0
1
φ
s/2
0
φ
s/4 1
1
φ
s/8
Bit 5: Counter Overflow Flag (CPOVF)
CPOVF flag indicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
CPOVF Description
0 Normal state (Initial value)
1 Indicates that an overflow has occurred in the counter