Renesas Hitachi H8S/2191, Hardware Manual, Page: 812 / 1065

Rev. 2.0, 11/00, page 785 of 1037
(2) Register Descriptions
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Register configuration
Table 28.23 shows the register configuration of the CFG frequency divider.
Table 28.23 Register Configuration
Name Abbrev. R/W Size Initial Value Address
DVCFG control register CDVC R/W Byte H'60 F'FD09A
CFG frequency division
register 1 CDIVR1 W Byte H'80 H'FD09B
CFG frequency division
register 2 CDIVR2 W Byte H'80 H'FD09C
DVCFG mask period
register CTMR W Byte H'FF H'FD09D
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DVCFG control register (CDVC)
0
0
1
0
W
2
0
W
3 4
0
W
5
1
6
—
—
1
7
W R
CMK CMN
W
DVTRG
0
R/W
*
MCGin CRF CPS1 CPS0
0
Note: * Only 0 can be written.
Bit :
Initial value :
R/W :
CDVC is an 8-bit register to control the capstan frequency division circuit.
It is initialized to H'60 by a reset, stand-by or module stop.
Bit 7: Mask CFG Flag (MCGin)
MCGin is a flag to indicate occurrence of a frequency division signal during the mask timer's
mask period. To clear it, write 0. To clear it by software, write 0 after reading 1. Also, setting
has the highest priority in this flag. If a condition setting the flag and 0 write occurs
simultaneously, the latter is nullified.
Bit 7
MCGin Description
0 CFG is in normal operation (Initial value)
1 Shows that DVCFG was detected during masking (runaway detected)
Bit 6: Reserved
No write in it is valid. If a read is attempted, 1 is read out.