Renesas Hitachi H8S/2191, Hardware Manual

Page: 385 / 1065

Rev. 2.0, 11/00, page 358 of 1037
17.1.4 Register Configuration
Table 17.2 shows the register configuration of the Timer X1.
Table 17.2 Register Configuration
Name Abbrev. R/W Initial Value Address
* 3
Timer interrupt enabling register TIER R/W H'00 H'D100
Timer control/status register X TCSRX R/ (W)
*
1
H'00 H'D101
Free running counter H FRCH R/W H'00 H'D102
Free running counter L FRCL R/W H'00 H'D103
Output comparing register AH OCRAH R/W H'FF H'D104
*
2
Output comparing register AL OCRAL R/W H'FF H'D105
* 2
Output comparing register BH OCRBH R/W H'FF H'D104
*
2
Output comparing register BL OCRBL R/W H'FF H'D105
* 2
Timer control register X TCRX R/W H'00 H'D106
Timer output comparing control register TOCR R/W H'00 H'D107
Input capture register AH ICRAH R H'00 H'D108
Input capture register AL ICRAL R H'00 H'D109
Input capture register BH ICRBH R H'00 H'D10A
Input capture register BL ICRBL R H'00 H'D10B
Input capture register CH ICRCH R H'00 H'D10C
Input capture register CL ICRCL R H'00 H'D10D
Input capture register DH ICRDH R H'00 H'D10E
Input capture register DL ICRDL R H'00 H'D10F
Notes: 1. Only 0 can be written to clear the flag for Bits 7 to 1. Bit 0 is readable/writable.
2. The addresses of the OCRA and OCRB are the same. Changeover between them
are to be made by use of the TOCR bit and OCRS bit.
3. Lower 16 bits of the address.