Renesas Hitachi H8S/2191, Hardware Manual

Page: 703 / 1065

Rev. 2.0, 11/00, page 676 of 1037
28.4.8 Cautions
(1) When both the 5-bit DFG counter and 16-bit timer counter are operating, the latter is not
cleared if input of DPG and DFG signals is stopped. This leads to free-running of the 16-bit
timer counter, and periodical detection of matching by the 16-bit timer counter. In such a
case, the period of the output from the HSW timing generator is independent from DPG or
DFG.
(2) Specify the mode setting bit (LOP) of the HSW mode register 2 (HSM2) immediately before
writing the FIFO data.
(3) Input the rising edge of DPG and DFG count edge at different timings. If the same timing
was input, counting up of DFG and clearing of the 5-bit DFG counter occurs simultaneously.
In this case, the latter will take precedence. This leads to the 5-bit DFG counter's lag by 1.
Figure 28.25 shows the input timing of DPG and DFG.
(4) If stop of the drum system is required when FIFO output is being used in the 20-stage output
mode, rewrite the SOFG bit of HSM2 register 0
→
1
→
0 by software, and initialize the
FIFO output stage to the FIFO1 side without fail. Also clear and rewrite the data of FIFO1
and FIFO2.
DPG
I ± T
P · FG
I > (1 state)
T
P · FG
DFG
Note: When the DFG counter takes count at the rising edges of DFG
Figure 28.25 Input Timing of DPG and DFG