Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 486 of 1037
23.3.4 Operation in Clock Synchronous Mode
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses,
making it suitable for high-speed serial communication.
Inside the SCI1, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 23.14 shows the general format for clock synchronous serial communication.
Don't care Don't care
One unit of transfer data (character or frame)
Bit 0
Serial
data
Synchronous
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
* *
Note: * High except in continuous transmit/reception
Figure 23.14 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, data on the transmission line is output from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the
serial clock.
In clock synchronous serial communication, one character consists of data output starting with
the LSB and ending with the MSB. After the MSB is output, the transmission line holds the
MSB state.
In clock synchronous mode, the SCI1 receives data in synchronization with the rising edge of the
serial clock.
(1) Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
(2) Clock
Either an internal clock generated by the built-in baud rate generator or an external serial
clock input at the SCK1 pin can be selected, according to the setting of the C/
$ bit in SMR1
and the CKE1 and CKE0 bits in SCR1. For details on SCI clock source selection, see table
23.9.
When the SCI1 is operated on an internal clock, the serial clock is output from the SCK1 pin.