Renesas Hitachi H8S/2191, Hardware Manual, Page: 502 / 1065

Rev. 2.0, 11/00, page 475 of 1037
(c) Serial Data Reception (Asynchronous Mode)
Figure 23.7 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
Yes
< End >
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR1
[4]
[5]
Clear RE bit in SCR1 to 0
Read ORER, PER,
FER flags in SSR1
Error handling
(Continued on next page)
[3]
Read receive data in RDR1, and clear
RDRF flag in SSR1 to 0
No
Yes
PER FER ORER=1
RDRF=1
All data received?
SCI1 initialization:
The SI1 pin is automatically designated as
the receive data input pin.
Receive error handling and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR1 to identify the
error. After performing the appropriate
error handling, ensure that the ORER,
PER, and FER flags are all cleared to 0.
Reception cannot be resumed if any of
these flags are set to 1. In the case of a
framing error, a break can be detected by
reading the value of the input port
corresponding to the SI1 pin.
SCI1 status check and receive data read:
Read SSR1 and check that RDRF = 1, then
read the receive data in RDR1 and clear
the RDRF flag to 0. Transition of the RDRF
flag from 0 to 1 can also be identified by an
RXI interrupt.
Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is received,
read the RDRF flag, read RDR1, and clear
the RDRF flag to 0.
[1]
[2][3]
[4]
[5]
Figure 23.7 Sample Serial Reception Data Flowchart (1)