Renesas Hitachi H8S/2191, Hardware Manual

Page: 843 / 1065

Rev. 2.0, 11/00, page 816 of 1037
(4) Servo Interrupt Request Register 2 (SIRQR2)
0
0
1
0
R/(W)
*
2 3 4 5 6
1
7
— — — — — —
— — — — — — R/(W)
*
IRRSNC IRRCTL
1 1 1 1 1
Note:
*
Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SIRQR2 displays an occurrence of an interrupt request of the servo section. If the interrupt
request occurred, the corresponding bit is set to 1.
SIRQR2 is an 8-bit readable/writable register. Writing 0 after reading 1 is allowed; no other
writing is allowed. It is initialized to H'FC by a reset, stand-by or module stop.
Bits 7 to 2: Reserved
No read or write is valid. If a read is attempted, an undetermined value is read out.
Bit 1: Vertical Sync Signal Interrupt Request Bit (IRRSNC)
Bit 1
IRRSNC Description
0 No interrupt request from the sync signal detector (VD, noise) (Initial value)
1 Interrupt requested from the sync signal detector (VD, noise)
Bit 0: CTL Signal Interrupt Request Bit (IRRCTL)
Bit 0
IRRCTL Description
0 No interrupt request from CTL (Initial value)
1 Interrupt requested from CTL