Renesas Hitachi H8S/2191, Hardware Manual, Page: 519 / 1065

Rev. 2.0, 11/00, page 492 of 1037
In serial reception, the SCI1 operates as described below.
[1] The SCI1 performs internal initialization in synchronization with serial clock input or output.
[2] The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI1 checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR1.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR1. If a
receive error is detected in the error check, the operation is as shown in table 23.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
[3] If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated.
Also, if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 23.19 shows an example of SCI1 operation in reception.
Bit 7
Serial
data
Synchronous
clock
1 frame
RDRF
ORER
ERI interrupt request
generated by
overrun error RXI interrupt
request
generated RDR1 data read and
RDRF flag cleared to 0
in RXI interrupt
handling routine RXI interrupt
request
generated
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 23.19 Example of SCI1 Operation in Reception
(d) Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
Figure 23.20 shows a sample flowchart for simultaneous serial transmit and receive
operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.