Renesas Hitachi H8S/2191, Hardware Manual, Page: 370 / 1065

Rev. 2.0, 11/00, page 343 of 1037
16.2.7 Timer R Load Register 2 (TMRL2)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR27
W
TMR26
W
TMR25
W
TMR24
W
TMR23
W
TMR22
W
TMR21
W
TMR20
Bit :
Initial value :
R/W :
The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load
value of the TMRU-2.
When a load value is set to the TMRL2, the same value will be set to the TMRU-2 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows or a CFG edge is detected during the course of the reload timer operation, the
TMRL2 value will be set to the counter.
When reset, the TMRL2 is initialized to H'FF.
16.2.8 Timer R Load Register 3 (TMRL3)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR37
W
TMR36
W
TMR35
W
TMR34
W
TMR33
W
TMR32
W
TMR31
W
TMR30
Bit :
Initial value :
R/W :
The timer R load register 3 (TMRL3) is an 8-bit write only register which works to set the load
value of the TMRU-3.
When a load value is set to the TMRL3, the same value will be set to the TMRU-3 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows or a DVCTL edge is detected, the TMRL2 value will be set to the counter.
(Reloading will be made by the underflowing signals when the DVCTL signal is selected as the
clock source, and reloading will be made by the DVCTL signals when the dividing clock is
selected as the clock source.)
When reset, the TMRL3 is initialized to H'FF.