Renesas Hitachi H8S/2191, Hardware Manual

Page: 736 / 1065

Rev. 2.0, 11/00, page 709 of 1037
(b) Lock detection
If error data was detected within the lock range set in the lock data register, the capstan lock
flag (CF-R/UNR) is set by the number of the times of occurrence of locking set by the
CFRCS1 and CFRCS0 bits, and an interrupt is requested (IRRCAP2) at the same time. The
number of the occurrence of locking (once to 4 times) can be specified when setting the flag.
Use the CFRCS1 and CFRCS0 bits for this purpose. Also, if bit 5 (CPHA bit) of the capstan
system digital filter control register (CFIC) is 0 (phased system digital filter computation off)
and the DPCNT bit is 1, turning on/off of the phase system digital filter computation can be
controlled automatically by the status of lock detection.
(c) Capstan system speed error detection counter
The capstan system speed error detection counter stops the counter and sets the overflow flag
(CFOVF) when overflow occurred. At the same time, it generates an interrupt request
(IRRCAP1). Clear CFOVF by writing 0 after reading 1. If setting the flag and writing 0
take place simultaneously, the latter is nullified.
(d) Interrupt request
IRRCAP1 is generated by the DVCFG signal latch and the overflow of the error detection
counter. IRRCAP2 is generated by detection of lock (after the detection of the number of
times of setting).
–value +value
Specified speed value
Latch data 0
(no error)
Preset value
Preset period
(2 counts)
Counter
Error data
latch signal
(DVCFG)
Preset data
load
Figure 28.33 Example of the Operation of the Capstan Speed Error Detection