Renesas Hitachi H8S/2191, Hardware Manual

Page: 1037 / 1065

Rev. 2.0, 11/00, page 1010 of 1037
H'FFF0: IRQ Edge Select Register IEGR: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0 0
7
R/W R/W R/W
IRQ4EG
R/W
IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG2
0
6
IRQ0 pin detected dege select bits
IRQ0 pin detected edge select
0 0 Interrupt request generaed at falling edge of IRQ0 pin input
IRQ0EG0 IRQ0EG1
1 0 Interrupt request generaed at rising edge of IRQ0 pin input
*
1 Interrupt request generaed at bath falling and rising edge of IRQ0 pin input
Note: * Don't care.
IRQ5 to IRQ1 pins detected edge select bits
Interrupt request generated at falling edge of IRQn pin input
Interrupt request generated at rising edge of IRQn pin input
0
1
(n = 5 to 1)
Bit :
Initial value :
R/W :
—
—
H'FFF1: IRQ Enable Register IENR: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0 0
7
R/W R/W R/W
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
6
IRQ5 to IRQ0 enable bits
IRQn interrupt is disabled
IRQn interrupt is enabled
0
1
(n = 5 to 0)
Bit :
Initial value :
R/W :
— —
— —