Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 453 of 1037
Bit 1 Bit 0
CKE1 CKE0 Description
Asynchronous mode Internal clock/SCK1 pin functions as I/O
port
* 1
0
Clock synchronous
mode Internal clock/SCK1 pin functions as serial
clock output
* 1
Asynchronous mode Internal clock/SCK1 pin functions as clock
output
* 2
0
1
Clock synchronous
mode Internal clock/SCK1 pin functions as serial
clock output
Asynchronous mode External clock/SCK1 pin functions as clock
input
* 3
0
Clock synchronous
mode External clock/SCK1 pin functions as serial
clock input
Asynchronous mode External clock/SCK1 pin functions as clock
input
* 3
1
1
Clock synchronous
mode External clock/SCK1 pin functions as serial
clock input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
23.2.7 Serial Status Register (SSR1)
7
TDRE
1
R/(W)
*
6
RDRF
0
R/(W)
*
5
ORER
0
R/(W)
*
4
FER
0
R/(W)
*
3
PER
0
R/(W)
*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI1,
and multiprocessor bits.
SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.