Renesas Hitachi H8S/2191, Hardware Manual

Page: 412 / 1065

Rev. 2.0, 11/00, page 385 of 1037
17.7 Precautions when Using the Timer X1
Pay great attention to the fact that the following competitions and operations occur during
operation of the Timer X1.
17.7.1 Competition between Writing and Clearing with the FRC
When a counter clearing signal is issued under the T2 state where the FRC is under the writing
cycle, writing into the FRC will not be effected and the priority will be given to clearing of the
FRC.
Figure 17.13 shows the timing chart in this case.
Address FRC address
Internal writing
signal
Counter clearing
signal
FRC N H'0000
T1 T2
Writing cycle with the FRC
Figure 17.13 Competition between Writing and Clearing with the FRC