Renesas Hitachi H8S/2191, Hardware Manual

Page: 176 / 1065

Rev. 2.0, 11/00, page 149 of 1037
End of erasing
START
Set SWE bit in FLMCR1
Set ESU bit in FLMCR2
Set E bit in FLMCR1
Wait (x) µs
Wait (y) µs
n = 1
Set EBR1, EBR2
Enable WDT
*
2
*
4
*
2
Wait (z) ms
*
2
Wait ( ) µs
*
2
Wait ( ) µs
*
2
Wait ( ) µs
Set block start address to
verify address
*
2
Wait ( ) µs
*
2
Wait ( ) µs
*
2
*
2
*
2
*
3
*
5
Start of erase
Clear E bit in FLMCR1
Clear ESU bit in FLMCR2
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait ( ) µs
Clear EV bit in FLMCR1
Clear SWE bit in FLMCR1
Disable WDT
Halt erase
*
1
Verify data =
all 1?
End of erasing of
all erase blocks?
Erase failure
Clear SWE bit in FLMCR1
n N?
NO
NO
NO
NO
YES
YES
YES
YES
Notes: 1.
2.
3.
4.
5.
Increment
address
n n+1
Last address
of block?
Preprogramming (setting erase block data to all 0) is not necessary.
The values of x, y, z, , , , , and N are listed in section 29.2.7, Flash Memory Characteristics.
Verify data is read in 16-bit (word) units.
Set only one bit in EBR1 or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 7.13 Erase/Erase-Verify Flowchart (Single-Block Erase)