Renesas Hitachi H8S/2191, Hardware Manual

Page: 88 / 1065

Rev. 2.0, 11/00, page 61 of 1037
Bits 5 and 4: Interrupt control modes 1 and 0 (INTM1, INTM0)
These bits are for selecting the interrupt control mode of the interrupt controller. For details of
the interrupt control modes, see section 6.4, Interrupt Operation.
Bit 5 Bit 4
INTM1 INTM0
Interrupt
Control Mode
Description
0 0 Interrupt is controlled by bit I (Initial value) 0
1 1 Interrupt is controlled by bits I and UI, and ICR
0 2 Cannot be used in this LSI 1
1 3 Cannot be used in this LSI
Bit 3: External Reset (XRST)
Indicates the reset source. When the watchdog timer is used, a reset can be generated by
watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to
1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 A reset is generated by watchdog timer overflow
1 A reset is generated by an external reset (Initial value)
Bits 2 and 1: NMI edge select 1 and 0 (NMIG1, 0)
Select the input edge for NMI interrupt.
Bit 2 Bit 1
NIMIEG1 NIMIEG0 Description
0 An interrupt request occurs at falling edge of NMI input (Initial value) 0
1 An interrupt request occurs at rising edge of NMI input
1
*
An interrupt request occurs at rising or falling edge of NMI input
Note: * Don't care
Bit 0: Reserved.