Renesas Hitachi H8S/2191, Hardware Manual

Page: 514 / 1065

Rev. 2.0, 11/00, page 487 of 1037
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however,
the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To
perform receive operations in units of one character, select an external clock as the clock
source.
(3) Data Transfer Operations
(a) SCI1 Initialization (Synchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI1 as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE
bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the
contents of RDR1.
Figure 23.15 shows a sample SCI1 initialization flowchart.
Wait
<Transfer start>
Start initialization
Set data transfer format
in SMR1 and SCMR1
No
Yes
Set value in BRR1
Clear TE and RE bits in SCR1 to 0
[2]
[3]
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE, and MPIE
bits
[4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in
SCR1 (TE, RE bits 0)
[1]
Set the clock selection in SCR1. Be sure to
clear bits RIE, TIE, TEIE, and MPIE, TE
and RE, to 0.
Set the data transfer format in SMR1 and
SCMR1.
Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1.
Also set the RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
[1]
[2]
[3]
[4]
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 23.15 Sample SCI Initialization Flowchart