Renesas Hitachi H8S/2191, Hardware Manual, Page: 404 / 1065

Rev. 2.0, 11/00, page 377 of 1037
17.3.2 Counting Timing of the FRC
The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the
inputting clock can be selected from among three different types of clocks (
φ
/4,
φ
/16 and
φ
/64)
and the DVCFG.
(1) In Case of Internal Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (
φ
/4,
φ
/16
and
φ
/64), generated by dividing the system clock (
φ
) can be selected. Figure 17.3 shows the
timing chart at this time.
FRC
Internal clock
FRC input
clock
N N-1 N+1
Figure 17.3 Count Timing in Case of Internal Clock Operation
(2) In Case of DVCFG Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected.
The DVCFG clock makes counting by use of the edge detecting pulse being selected by the
CFG dividing timer.
Figure 17.4 shows the timing chart at this time.
FRC
CFG
FRC input
clock
N N+1
DVCFG
Figure 17.4 Count Timing in Case of CFG Clock Operation