Renesas Hitachi H8S/2191, Hardware Manual, Page: 701 / 1065

Rev. 2.0, 11/00, page 674 of 1037
After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of
FIFO2 is output. After the pattern data is output, the pointer is decremented by 1. Care is
required, however, because matching of t
A0
is not detected until data is written in FIFO2.
Matching of t
B0
also is not detected until data is written in FIFO1 again.
(2) Example of operation in loop mode
(a) Set the number of loop stages in the HSLP register (e.g. HSLP = H'44)
(b) Write the output pattern data (PA0) to FPDRA.
(c) Write the output timing (t
A1
) to FTPRA. t
A1
is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
(d) Repeat the steps in the same way, until PA1, PA2, etc., are set.
(e) Write the output pattern data (PB0) to FPDRB.
(f) Write the output timing (t
B1
) to FTPRB. t
B1
is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
(g) Repeat the steps in the same way, until PB1, PB2, etc., are set.
From (c), the pattern data PA0 is output.
If t
A1
matches the timer counter, the pattern data PA1 is output.
If t
A2
matches the timer counter, the pattern data PA2 is output.
.
.
.
If t
A4
matches the timer counter, the pattern data PA4 is output.
If t
A5
matches the timer counter, the pattern data PB0 is output.
If t
B1
matches the timer counter, the pattern data PB1 is output.
.
.
.
If t
B4
matches the timer counter, the pattern data PB4 is output.
If t
B5
matches the timer counter, the pattern data PA0 is output.
.
.
.