Renesas Hitachi H8S/2191, Hardware Manual, Page: 728 / 1065

Rev. 2.0, 11/00, page 701 of 1037
28.8 Capstan Speed Error Detector
28.8.1 Overview
Capstan speed control operates so as to hold the capstan motor at a constant revolution speed, by
measuring the period of the CFG signal. A digital counter detects the speed deviation from a
preset value. The speed error data is added to phase error data in a digital filter. This filter
controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase
of the capstan motor.
The CFG input signal is downloaded by the comparator circuit, then reshaped into a square wave
by a reshaping circuit, divided by the CFG divider, and sent to the speed error detector as the
DVCFG signal.
The speed error detector uses the system clock to measure the period of the DVCFG signal, and
detects the deviation from a preset data value. The preset data is the value that would result
from measuring the DVCFG signal period with the clock signal if the capstan motor was running
at the correct speed.
The error detector operates by latching a counter value when it detects an edge of the DVCFG
signal. The latched count provides 16 bits of speed error data for the digital filter to operate on.
The digital filter adds the speed error data to phase error data from the capstan phase control
system, then sends the result to the pulse-width modulator as capstan error data.
28.8.2 Block Diagram
Figure 28.32 shows a block diagram of the capstan speed error detector.