Renesas Hitachi H8S/2191, Hardware Manual

Page: 64 / 1065

Rev. 2.0, 11/00, page 37 of 1037
Table 2.5 Logic Instructions
Instruction Size
*
Function
AND B/W/L Rd
∧
Rs
→
Rd, Rd
∧
#IMM
→
Rd
Performs a logical AND operation on a general register and
another general register or immediate data
OR B/W/L Rd
∨
Rs
→
Rd, Rd
∨
#IMM
→
Rd
Performs a logical OR operation on a general register and
another general register or immediate data
XOR B/W/L Rd
⊕
Rs
→
Rd, Rd
⊕
#IMM
→
Rd
Performs a logical exclusive OR operation on a general register
and another general register or immediate data
NOT B/W/L ~ Rd
→
Rd
Takes the one's complement (logical complement) of general
register contents
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size
*
Function
SHAL
SHAR B/W/L Rd (shift)
→
Rd
Performs an arithmetic shift on general register contents
A 1-bit or 2-bit shift is possible
SHLL
SHLR B/W/L Rd (shift)
→
Rd
Performs a logical shift on general register contents
A 1-bit or 2-bit shift is possible
ROTL
ROTR B/W/L Rd (rotate)
→
Rd
Rotates general register contents
1-bit or 2-bit rotation is possible
ROTXL
ROTXR B/W/L Rd (rotate)
→
Rd
Rotates general register contents through the carry flag
1-bit or 2-bit rotation is possible
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword