Renesas Hitachi H8S/2191, Hardware Manual, Page: 556 / 1065

Rev. 2.0, 11/00, page 529 of 1037
Bits 5 to 3: Transfer Clock Select (CKS2 to CKS0)
These bits, together with the IICX bit in the STCR register, select the serial clock frequency in
master mode. They should be set according to the required transfer rate.
STCR
Bit 6
Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock
φ
= 5 MHz
φ
= 8 MHz
φ
= 10 MHz
0
φ
/28 179 kHz 286 kHz 357 kHz 0
1
φ
/40 125 kHz 200 kHz 250 kHz
0
φ
/48 104 kHz 167 kHz 208 kHz
0
1
1
φ
/64 78.1 kHz 125 kHz 156 kHz
0
φ
/80 62.5 kHz 100 kHz 125 kHz 0
1
φ
/100 50.0 kHz 80.0 kHz 100 kHz
0
φ
/112 44.6 kHz 71.4 kHz 89.3 kHz
0
1
1
1
φ
/128 39.1 kHz 62.5 kHz 78.1 kHz
0
φ
/56 89.3 kHz 143 kHz 179 kHz 0
1
φ
/80 62.5 kHz 100 kHz 125 kHz
0
φ
/96 52.1 kHz 83.3 kHz 104 kHz
0
1
1
φ
/128 39.1 kHz 62.5 kHz 78.1 kHz
0
φ
/160 31.3 kHz 50.0 kHz 62.5 kHz 0
1
φ
/200 25.0 kHz 40.0 kHz 50.0 kHz
0
φ
/224 22.3 kHz 35.7 kHz 44.6 kHz
1
1
1
1
φ
/256 19.5 kHz 31.3 kHz 39.1 kHz