Renesas Hitachi H8S/2191, Hardware Manual, Page: 320 / 1065

Rev. 2.0, 11/00, page 293 of 1037
12.2.2 Timer Counter A (TCA)
0
0
1
0
R
2
0
R
3
0
4 5 6 7
R R
TCA3
0
R
TCA4
0
R
TCA5
0
R
TCA6
0
R
TCA7 TCA2 TCA1 TCA0
Bit :
Initial value :
R/W :
The timer counter A (TCA) is an 8-bit up-counter which counts up on inputs from the internal
clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA
When the TCA overflows, the TMAOV bit of the TMA is set to 1.
The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11.
The TCA is always readable. When reset, the TCA will be initialized into H'00.
12.2.3 Module Stop Control Register (MSTPCR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop
Mode. When reset, the MSTPCR will be initialized into H'FFFF.
Bit 7: Module Stop (MSTP15)
This bit works to designate the module stop mode for the Timer A.
MSTPCRH
Bit 7
MSTP15 Description
0 Cancels the module stop mode of the Timer A
1 Sets the module stop mode of the Timer A (Initial value)