Renesas Hitachi H8S/2191, Hardware Manual

Page: 747 / 1065

Rev. 2.0, 11/00, page 720 of 1037
28.10.3 Register Descriptions
(1) Register Configuration
Table 28.13 shows the register configuration of X-value adjustment and tracking adjustment
circuits.
Table 28.13 Register Configuration
Name Abbrev. R/W Size Initial Value Address *
X-value and TRK-value
control register XTCR R/W Byte H'80 H'FD074
X-value data register XDR W Word H'F000 H'FD070
TRK-value data register TRDR W Word H'F000 H'FD072
(2) X-value and TRK-value Control Register (XTCR)
0
0
1
0
R/W
2
0
W
3
0
4
0
W
5
0
6
0
7
—
— R/W W W
AT/MU
W
CAPRF TRK/X EXC/REF XCS DVREF1 DVREF0
1
Bit :
Initial value :
R/W :
XTCR is an 8-bit register to determine the X-value and TRK-value adjustment circuits. Bits 6 to
2 are write-only bits. No read is valid. If a read is attempted, an undetermined value is read out.
Bits 1 and 0 are readable/writable bits. XTCR accepts only a byte access. If a word access is
attempted, operation is unassured.
It is initialized to H'80 by a reset, stand-by or module stop.
Bit 7: Reserved
No write is valid. If a read is attempted, an undetermined value is read out.
Bit 6: External Sync Signal Edge Selection Bit (CAPRF)
Selects the EXCAP edge when a selection is made to generate external sync signals.
Bit 6
CAPRF Description
0 Signal generated at the rising edge of EXCAP (Initial value)
1 Signal generated at both edges of EXCAP