Renesas Hitachi H8S/2191, Hardware Manual

Page: 554 / 1065

Rev. 2.0, 11/00, page 527 of 1037
25.2.4 I
2
C Bus Mode Register (ICMR)
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
Bit :
Initial value :
R/W :
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency
and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written
and read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset.
Bit 7: MSB-First/LSB-First Select (MLS)
Selects whether data is transferred MSB-first or LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the
LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS
= 1.
Do not set this bit to 1 when the I
2
C bus format is used.
Bit 7
MLS Description
0 MSB-first (Initial value)
1 LSB-first