Renesas Hitachi H8S/2191, Hardware Manual

Page: 662 / 1065

Rev. 2.0, 11/00, page 635 of 1037
28.3.5 Description of Operation
(1) Operation of REF30 Signal Generators
The REF30 signal generators generate the reference signals required to control the phase of
the drum and capstan.
To generate REF30 signals, set the half-period value to the reference period register 1 (RFD)
corresponding to the 50% duty cycle. When in playback, REF30 signals are generated by
operating REF30 signal generator in free-run. The generator has the external signal
synchronization function built-in, and if bit 4 (REX) of the reference period mode register
(RFM) is set to 1, it generates REF30 signals from external signals (EXTTRG).
In record mode, the reference signals are generated from the VD signal generated in the sync
signal detection circuit. Any VD drop-out caused by weak field intensity, etc., is
compensated by a set value of RFD. To cope with the VD noises, the generator performs
automatically the VD masking for a time period about 75% of the RFD setting after REF30
signal was changed due to VD. In record mode, the generation of the reference signals either
by VD or free-run operation can be controlled automatically or by software, using the V
noise detection signal detected in the sync signal detection circuit. Select which is used by
setting bit 6 (VNA) or 5 (CVS) of RFM.
The phase of the toggle output of the REF30 signal is cleared to L level when the signal
mode transits from PB to REC (ASM). Also the frame servo function can be set, allowing to
control the phase of REF30 signals with the field signal detected in the sync signal detection
circuit. Use bit 2 (OD/EV) of RFM for such control.
See section 28.13.5(2), CTL Mode Register (CTLM) as for switching over between PB,
ASM and REC.
(2) Operation of the Mask Circuit
The REF30 signal generators have a toggle mask circuit and counter mask (counter set signal
mask) circuit built-in. Each mask circuit masks irregular VD signals which may occur when
the VD signal is unstable because of weak field intensity, etc., in record mode.
The toggle mask and counter mask circuits mask the VD automatically for about 75% of
double the time period set in the reference period register 1 (RFD) after a VD signal was
detected (see figure 28.9). If a VD signal dropped out and V was compensated, the toggle
mask circuit begins masking. The counter mask circuit does not do so for about 25% of the
time period. If a VD signal was detected during such time period, it does masking for about
75% of the time period. If not detected, it does for the same time period after V was
compensated (see figures 28.10 and 28.11).