Renesas Hitachi H8S/2191, Hardware Manual, Page: 390 / 1065

Rev. 2.0, 11/00, page 363 of 1037
17.2.4 Timer Interrupt Enabling Register (TIER)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/W R/W R/W
ICICE
R/W
ICIBE
0
R/W
ICIAE ICIDE OCIAE OCIBE OVIE ICSA
Bit :
Initial value :
R/W :
The TIER is an 8-bit read/write register which works to control permission/prohibition of
respective interrupt requests.
The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Bit 7: Enabling the Input Capture Interrupt A (ICIAE)
This bit works to permit/prohibit interrupt requests (ICIA) by the ICFA when the ICFA of the
TCSRX is being set to 1.
Bit 7
ICIAE Description
0 Prohibits interrupt requests (ICIA) by the ICFA (Initial value)
1 Permits interrupt requests (ICIA) by the ICFA
Bit 6: Enabling the Input Capture Interrupt B (ICIBE)
This bit works to permit/prohibit interrupt requests (ICIB) by the ICFB when the ICFB of the
TCSRX is being set to 1.
Bit 6
ICIBE Description
0 Prohibits interrupt requests (ICIB) by the ICFB (Initial value)
1 Permits interrupt requests (ICIB) by the ICFB
Bit 5: Enabling the Input Capture Interrupt C (ICICE)
This bit works to permit/prohibit interrupt requests (ICIC) by the ICFC when the ICFC of the
TCSRX is being set to 1.
Bit 5
ICICE Description
0 Prohibits interrupt requests (ICIC) by the ICFC (Initial value)
1 Permits interrupt requests (ICIC) by the ICFC