Renesas Hitachi H8S/2191, Hardware Manual, Page: 473 / 1065

Rev. 2.0, 11/00, page 446 of 1037
23.2.3 Transmit Shift Register (TSR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit :
R/W :
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI1 first transfers transmit data from TDR1 to TSR,
then sends the data to the SO1 pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR1 to
TSR, and transmission started, automatically. However, data transfer from TDR1 to TSR is not
performed if the TDRE bit in SSR1 is set to 1.
TSR cannot be directly read or written to by the CPU.
23.2.4 Transmit Data Register (TDR1)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
TDR1 is an 8-bit register that stores data for serial transmission.
When the SCI1 detects that TSR is empty, it transfers the transmit data written in TDR1 to TSR
and starts serial transmission. Continuous serial transmission can be carried out by writing the
next transmit data to TDR1 during serial transmission of the data in TSR.
TDR1 can be read or written to by the CPU at all times.
TDR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.