Renesas Hitachi H8S/2191, Hardware Manual

Page: 131 / 1065

Rev. 2.0, 11/00, page 104 of 1037
6.2.5 IRQ Status Register (IRQR)
0
0
1
0
R/(W)
*
2
0
R/(W)
*
3
0
4
0
R/(W)
*
5
0 0
7
R/(W)
*
R/(W)
*
R/(W)
*
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
6
— —
— —
Note: * Only 0 can be written, to clear the flag.
Bit :
Initial value :
R/W :
IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
IRQR is initialized to H'00 by a reset.
Bit 7 and 6: Reserved
Do not write 1 to them.
Bits 5 to 0: IRQ5 to IRQ0 Flags
These bits indicate the status of IRQ5 to IRQ0 interrupt requests.
Bit n
IRQnF Description
0 [Clearing conditions] (Initial value)
Cleared by reading IRQnF set to 1, then writing 0 in IRQnF
When IRQn interrupt exception handling is executed
1 [Setting conditions]
(1) When a falling edge occurs in
,54Q
input while falling edge detection is set
(IRQnEG = 0)
(2) When a rising edge occurs in
,54Q
input while rising edge detection is set
(IRQnEG = 0)
(3) When a falling or rising edge occurs in
,54
input while both-edge detection is
set (IRQ0EG1 = 1)
(n = 5 to 0)