Renesas Hitachi H8S/2191, Hardware Manual

Page: 212 / 1065

Rev. 2.0, 11/00, page 185 of 1037
8.3.3 Erase Block Registers 1 (EBR1)
7
—
0
—
6
—
0
—
5
EB13
0
R/W
4
EB12
0
R/W
3
EB11
0
R/W
0
EB8
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
Bit
EBR1
Initial value
R/W
:
:
:
:
EBR1 is a register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module
stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is
input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the
corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1
or EBR2 (more than one bit cannot be set).
The flash memory block configuration is shown in table 8.3.
8.3.4 Erase Block Registers 2 (EBR2)
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit
EBR2
Initial value
R/W
:
:
:
:
EBR2 is a register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module
stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is
input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the
corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1
or EBR2 (more than one bit cannot be set).
The flash memory block configuration is shown in table 8.4.