Renesas Hitachi H8S/2191, Hardware Manual, Page: 767 / 1065

Rev. 2.0, 11/00, page 740 of 1037
28.12 Additional V Signal Generator
28.12.1 Overview
The circuit described in this section outputs an additional vertical sync signal to take the place of
Vsync in special playback. It is activated at both edges of the HSW signal output by the head-
switch timing generator. The head-switch timing generator also outputs a Vpulse signal
containing the additional vertical sync pulse itself, and an Mlevel signal that defines the width of
the additional vertical sync signal including the equalizing pulses.
The additional V signal is output at a three-level output pin (Vpulse).
Figure 28.43 shows the additional V signal control circuit.
Csync
Additional V pulse
OSCH
Vpulse signal
Mlevel signal
Sync detector
HSW timing
generator
Additional V
pulse generator
Figure 28.43 Additional V Pulse Control Circuit
(a) HSW timing generator
This circuit generates signals that are synchronized with head switching. It should be
programmed to generate the Mlevel and Vpulse signals at edges of the HSW signal
(VideoFF). For details, see section 28.4, HSW (Head-switch) Timing Generator.
(b) Sync detector
This circuit detects pulses of the width specified by VTR or HTR from the signal input at the
Csync pin and generates an internal horizontal sync signal (OSCH). The sync detector has
an interpolation function, so OSCH has a regular period even if there are horizontal sync
dropouts in the signal received at the pin. For details, see section 28.15, Sync Signal
Detector.