Renesas Hitachi H8S/2191 Hardware Manual Download Page 156

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Rev. 2.0, 11/00, page 129 of 1037

(3) Differences between Boot Mode and User Program Mode

Table 7.1

Differences between Boot Mode and User Program Mode

Boot Mode

User Program Mode

Entire memory erase

Yes

Block erase

Yes

Programming control program

Program/program-verify

Erase/erase-verify
Program/program-verify

Note:

To be provided by the user, in accordance with the recommended algorithm.

(4) Block Configuration

The flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte
block, one 28-kbyte block, and four 1-kbyte blocks.

8k bytes

Address H'00000

Address H'1FFFF

128 kbytes

32 kbytes

128-kbyte version

32 kbytes

28 kbytes

1 kbyte
1 kbyte
1 kbyte
1 kbyte

16 kbytes

8k bytes

Figure 7.6 Flash Memory Block Configuration

Summary of Contents for Hitachi H8S/2191

Page 1: ...tc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Than...

Page 2: ...ed here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or err...

Page 3: ...194C Series H8S 2194 F ZTAT H8S 2194C F ZTAT H8S 2194 HD6432194 HD64F2194 H8S 2193 HD6432193 H8S 2192 HD6432192 H8S 2191 HD6432191 H8S 2194C HD6432194C HD64F2194C H8S 2194B HD6432194B H8S 2194A HD6432...

Page 4: ...f bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the produ...

Page 5: ...ode Timer L PSU 12 bit PWM added Sleep and Watch modes of I O amended 79 4 4 1 Sleep Mode Description amended Other supporting modules excluding the servo circuit and 12 bit PWM do not stop 80 4 5 1 M...

Page 6: ...7 8 Boot Mode Execution Procedure Flow amended 141 Table 7 6 System Clock Frequencies for which Automatic Adjustment of This LSI Bit Rate is Possible 2400 bps transfer bit rate deleted 142 7 4 1 Boot...

Page 7: ...iption amended 336 16 2 1 Timer R Mode Register 1 TMRM1 Bit 0 description amended 416 20 2 1 12 Bit PWM Control Registers CPWCR DPWCR Initialization description amended 419 20 2 2 12 Bit PWM Data Regi...

Page 8: ...Descriptions 5 CTL Gain Control Register CTLGR Bits 3 to 0 CTL Amplifier Gain Setting Bits CTLGR3 to 0 values of CTL output gain amended 627 28 3 2 Block Diagram Figure 28 6 REF30 Signal Generator am...

Page 9: ...ster MSTPCR Added 819 to 860 29 Electrical Characteristics Description amended due to introduction of the H8S 2194C series 861 to 909 Appendix A Instruction Set Notes on TAS instruction added 917 to 1...

Page 10: ...ion 24 2 4 1 Overview 24 2 4 2 General Registers 25 2 4 3 Control Registers 26 2 4 4 Initial Register Values 27 2 5 Data Formats 28 2 5 1 General Register Data Formats 28 2 5 2 Memory Data Formats 30...

Page 11: ...w 67 4 1 1 Register Configuration 71 4 2 Register Descriptions 72 4 2 1 Standby Control Register SBYCR 72 4 2 2 Low Power Control Register LPWRCR 74 4 2 3 Timer Register A TMA 76 4 2 4 Module Stop Con...

Page 12: ...Diagram 98 6 1 3 Pin Configuration 99 6 1 4 Register Configuration 99 6 2 Register Descriptions 100 6 2 1 System Control Register SYSCR 100 6 2 2 Interrupt Control Registers A to D ICRA to ICRD 101 6...

Page 13: ...ster STCR 137 7 4 On Board Programming Modes 138 7 4 1 Boot Mode 139 7 4 2 User Program Mode 144 7 5 Programming Erasing Flash Memory 145 7 5 1 Program Mode 145 7 5 2 Program Verify Mode 146 7 5 3 Era...

Page 14: ...amming Erasing Flash Memory 195 8 5 1 Program Mode n 1 for addresses H 0000 to H 1FFFF and n 2 for addresses H 20000 to H 3FFFF 195 8 5 2 Program Verify Mode n 1 for addresses H 00000 to H 1FFFF and n...

Page 15: ...1 Connecting a Crystal Resonator 226 10 3 2 External Clock Input 228 10 4 Duty Adjustment Circuit 231 10 5 Medium Speed Clock Divider 231 10 6 Bus Master Clock Selection Circuit 231 10 7 Subclock Osci...

Page 16: ...Port 5 267 11 7 1 Overview 267 11 7 2 Register Configuration 267 11 7 3 Pin Functions 271 11 7 4 Pin States 272 11 8 Port 6 273 11 8 1 Overview 273 11 8 2 Register Configuration 274 11 8 3 Pin Functi...

Page 17: ...2 3 Timer Load Register B TLB 299 13 2 4 Port Mode Register 5 PMR5 300 13 2 5 Module Stop Control Register MSTPCR 300 13 3 Operation 302 13 3 1 Operation as the Interval Timer 302 13 3 2 Operation as...

Page 18: ...egisters 334 16 2 1 Timer R Mode Register 1 TMRM1 334 16 2 2 Timer R Mode Register 2 TMRM2 336 16 2 3 Timer R Control Status Register TMRCS 339 16 2 4 Timer R Capture Register 1 TMRCP1 341 16 2 5 Time...

Page 19: ...ion 376 17 3 1 Operation of the Timer X1 376 17 3 2 Counting Timing of the FRC 377 17 3 3 Output Comparing Signal Outputting Timing 378 17 3 4 FRC Clearing Timing 378 17 3 5 Input Capture Signal Input...

Page 20: ...5 19 1 Overview 405 19 1 1 Features 405 19 1 2 Block Diagram 405 19 1 3 Pin Configuration 406 19 1 4 Register Configuration 406 19 2 Register Descriptions 407 19 2 1 Bit PWM Data Registers 0 1 2 and 3...

Page 21: ...gister PCSR 434 22 2 3 Port Mode Register 1 PMR1 437 22 3 Noise Cancel Circuit 437 22 4 Operation 438 22 4 1 Prescalar S PSS 438 22 4 2 Prescalar W PSW 439 22 4 3 Stable Oscillation Wait Time Count 43...

Page 22: ...Register STAR 502 24 2 2 Ending Address Register EDAR 502 24 2 3 Serial Control Register 2 SCR2 503 24 2 4 Serial Control Status Register 2 SCSR2 504 24 2 5 Module Stop Control Register MSTPCR 507 24...

Page 23: ...7 26 2 1 Software Triggered A D Result Register ADR 577 26 2 2 Hardware Triggered A D Result Register AHR 577 26 2 3 A D Control Register ADCR 579 26 2 4 A D Control Status Register ADCSR 582 26 2 5 T...

Page 24: ...Input Signals 625 28 3 Reference Signal Generators 626 28 3 1 Overview 626 28 3 2 Block Diagram 626 28 3 3 Register Configuration 628 28 3 4 Register Descriptions 629 28 3 5 Description of Operation...

Page 25: ...tector 710 28 9 1 Overview 710 28 9 2 Block Diagram 710 28 9 3 Register Configuration 712 28 9 4 Register Descriptions 713 28 9 5 Description of Operation 716 28 10 X Value and Tracking Adjustment Cir...

Page 26: ...798 28 15 6 Noise Detection 806 28 15 7 Sync Signal Detector Activation 809 28 16 Servo Interrupt 810 28 16 1 Overview 810 28 16 2 Register Configuration 810 28 16 3 Register Description 810 28 17 Mod...

Page 27: ...haracteristics of HD6432194 HD6432193 HD6432192 HD6432191 HD6432194C HD6432194B and HD6432194A 858 Appendix A Instruction Set 861 A 1 Instructions 861 A 2 Instruction Codes 872 A 3 Operation Code Map...

Page 28: ...he object code level facilitating migration from the H8 300 H8 300L or H8 300H Series The H8S 2194 Series and H8S 2194C Series are incorporated with digital servo circuit ROM RAM seven types of timers...

Page 29: ...16 32 bit transfer arithmetic and logic instructions Unsigned signed multiply and divide instructions Powerful bit manipulation instructions CPU operating modes Advanced mode 16 Mbyte address space Ti...

Page 30: ...nternal clock and DVCFG Two output compare outputs Four input capture inputs 7 Watchdog timer Functions as watchdog timer or 8 bit interval timer Generates reset signal or NMI at overflow Prescaler un...

Page 31: ...Supports two slave addresses A D converter Resolution 10 bits Input 12 channels High speed conversion 13 4 s minimum conversion time 10 MHz operation Sample and hold function A D conversion can be act...

Page 32: ...se generator 8 to 10 MHz Subclock pulse generator 32 768 kHz Packages 112 pin plastic QFP FP 112 Product lineup Product Name ROM RAM H8S 2194C 256 kbytes 6 kbytes H8S 2194B 192 kbytes 6 kbytes H8S 219...

Page 33: ...WM0 P36 BUZZ P31 STRB P37 TMO P30 CS P34 PWM2 P43 FTIC P45 FTOA P42 FTIB P46 FTOB P41 FTIA P47 P40 PWM14 P44 FTID P51 P53 TRIG P50 ADTRG P52 TMBI P73 PPG3 P75 PPG5 P72 PPG2 P76 PPG6 P71 PPG1 P77 PPG7...

Page 34: ...CTL 82 4 CTLBias 81 5 CTLFB 80 6 CTLAmp o 79 7 CTLSMT i 78 8 CFG 77 9 SV CC 76 10 AV CC 75 11 P00 AN0 74 12 P01 AN1 73 13 P02 AN2 72 14 P03 AN3 71 15 P04 AN4 70 16 P05 AN5 69 17 P06 AN6 68 18 P07 AN7...

Page 35: ...g power supply Power supply pin for A D converter It should be connected to the system power supply 5V when the A D converter is not used Power supply AVss 23 Input Analog ground Ground pin for A D co...

Page 36: ...nterrupts 10 63 Input Nonmaskable interrupt Nonmaskable interrupt input pin for which rising edge sense falling edge sense or both edges sense are selectable 60 Input Input capture input Input capture...

Page 37: ...WM square waveform output Output pin for waveform generated by 14 bit PWM SCK1 SCK2 48 53 Input output SCI clock input output Clock input pins for SCI 1 and 2 SI1 SI2 46 51 Input SCI receive data inpu...

Page 38: ...PWM 102 Output Drum mix 12 bit PWM output pin giving result of drum speed error and phase error after filtering Vpulse 110 Output Additional V pulse Three level output pin for additional V signal sync...

Page 39: ...al port when not used EXCTL PS4 106 Input input output External CTL input Input pin for external CTL signal This pin can also be used as a general port when not used Csync 98 Input Mixed sync signal i...

Page 40: ...8 bit I O pins P47 to P40 35 to 28 Input output Port 4 8 bit I O pins P53 to P50 27 to 24 Input output Port 5 4 bit I O pins P67 to P60 79 to 72 Input output Port 6 8 bit I O pins P77 to P70 89 to 85...

Page 41: ...H8S 2193 3 kbytes H8S 2192 3 kbytes H8S 2191 3 kbytes Timer J Five operating modes TMJ 2 input clock sources PSS 16384 2048 or 1024 underflow of TMJ 1 external clock IRQ2 Four operating modes TMJ 2 in...

Page 42: ...een 8 bit registers or eight 32 bit registers Sixty five basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight...

Page 43: ...the H8S 2600 CPU Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported only by the H8S 2600 CPU Number of execution states The number of execution states of the MULXU and M...

Page 44: ...ave been added Instructions for saving and restoring multiple registers have been added A test and set instruction has been added Higher speed Basic instructions execute twice as fast 2 1 4 Difference...

Page 45: ...is LSI Figure 2 1 CPU Operating Modes 1 Normal Mode The exception vector table and stack have the same structure as in the H8 300 CPU a Address Space A maximum address space of 64 kbytes can be access...

Page 46: ...05 H 0006 H 0007 H 0008 H 0009 H 000A H 000B Reset exception vector Exception vector 1 Exception vector 2 Exception vector table Reserved for system use Figure 2 2 Exception Vector Table Normal Mode T...

Page 47: ...ption Handling PC 16 bits CCR CCR PC 16 bits SP SP Note Ignored when returning Figure 2 3 Stack Structure in Normal Mode 2 Advanced Mode a Address Space Linear access is provided to a 16 Mbyte maximum...

Page 48: ...exception vector Reserved for system use Reserved Exception vector 1 Reserved H 00000010 H 00000008 H 00000007 Figure 2 4 Exception Vector Table Advanced Mode The memory indirect addressing mode aa 8...

Page 49: ...nd condition code register CCR are pushed onto the stack in exception handling they are stored as shown in figure 2 5 The extended control register EXR is not pushed onto the stack For details see sec...

Page 50: ...ccess to a maximum 64 kbyte address space in normal mode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode b Advanced mode H 0000 H FFFF H 00000000 H FFFFFFFF H 00FFFFFF a...

Page 51: ...R2L R3L R4L R5L R6L R7L General Registers Rn and Extended Registers En Control Registers CR Legend SP PC EXR T I2 to I0 CCR I UI ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 SP I UI H U N Z V C CCR 7 6 5 4 3 2 1...

Page 52: ...registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These regis...

Page 53: ...r In this LSI this register does not affect operation Bit 7 Trace Bit T This bit is reserved In this LSI this bit does not affect operation Bits 6 to 3 Reserved These bits are reserved They are always...

Page 54: ...indicate non zero data Bit 1 Overflow Flag V Set to 1 when an arithmetic overflow occurs and cleared to 0 otherwise Bit 0 Carry Flag C Set to 1 when a carry occurs and cleared to 0 otherwise Used by...

Page 55: ...two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 10 shows the data formats in general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Upper digit Lower digit Don t care Don t care...

Page 56: ...Word data Word data Longword data General Register Rn En ERn Data format ERn En Rn RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Mos...

Page 57: ...but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches 7 0 7 6 5 4 3 2 1 0 MSB LSB MSB MSB LSB LSB Address...

Page 58: ...OR XOR NOT BWL 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR BWL 8 Bit manipulation RSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RTS 5 System...

Page 59: ...BS INC DEC DAA DAS NEG EXTU EXTS TAS 2 MOVFPE MOVTPE 1 MULXU DIVXU MULXS DIVXS AND OR XOR ANDC ORC XORC NOT Bcc BSR JMP JSR RTS TRAPA RTE SLEEP LDC STC NOP Shift Bit manipulation Block data transfer D...

Page 60: ...nation operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program coun...

Page 61: ...e used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the st...

Page 62: ...or 2 Byte operands can be incremented or decremented by 1 only ADDS SUBS B Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B W Rd decimal adj...

Page 63: ...nt arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword si...

Page 64: ...he one s complement logical complement of general register contents Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Function SHAL SHAR B W L...

Page 65: ...fied bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bi...

Page 66: ...ate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the inverse of a specified bit in a general register...

Page 67: ...specified address JSR Branches to a subroutine at a specified address RTS Returns from a subroutine Mnemonic Description Condition BRA BT Always True Always BRN BF Never False Never BHI HIgh CVZ 0 BL...

Page 68: ...m and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size transfers are performed...

Page 69: ...ntil R4L 0 else next EEPMOV W if R4 0 then Repeat ER5 er6 R4 1 R4 Until R4 0 else next Transfers a data block according to parameters set in general registers R4L or R4 ER5 and ER6 R4L or R4 size of b...

Page 70: ...ve address extension and condition field op cc EA disp BRA d 16 etc Figure 2 12 Instruction Formats Examples 1 Operation Field Indicates the function of the instruction the addressing mode and the ope...

Page 71: ...pulation then write back the byte of data Caution is therefore required when using these instructions on a register containing write only bits or a port The BCLR instruction can be used to clear inter...

Page 72: ...gister indirect with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 aa 32 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 1 Register Direct Rn...

Page 73: ...d access For word or longword access the register value should be even 5 Absolute Address aa 8 aa 16 aa 24 or aa 32 The instruction code contains the absolute address of a memory operand The absolute...

Page 74: ...t instruction so the possible branching range is 126 to 128 bytes 63 to 64 words or 32766 to 32768 bytes 16383 to 16384 words from the branch instruction The resulting value should be an even number 8...

Page 75: ...ccessed or an instruction code to be fetched at the address preceding the specified address For further information see section 2 5 2 Memory Data Formats 2 7 2 Effective Address Calculation Table 2 13...

Page 76: ...op 24 23 Don t care 3 Register indirect with displacement d 16 ERn or d 32 ERn General register contents Sign extension disp 31 0 31 0 31 0 op r disp Don t care 24 23 4 Register indirect with post in...

Page 77: ...8 aa 16 aa 32 31 0 8 7 aa 24 31 0 16 15 31 0 31 0 op abs op abs abs op op abs H FFFF 24 23 Don t care Don t care Don t care Don t care 24 23 24 23 24 23 Sign exten sion 6 Immediate xx 8 xx 16 xx 32 op...

Page 78: ...e Address Calculation Effective Address EA 8 Memory indirect aa 8 Normal mode 0 0 31 8 7 0 15 H 000000 31 0 16 15 op abs abs Memory contents H 00 24 23 Don t care Advanced mode 31 0 31 8 7 0 abs H 000...

Page 79: ...porting modules have been initialized and are stopped Exception handling state A transient state in which the CPU changes the normal processing flow in response to a reset interrupt or trap instructio...

Page 80: ...t state occurs whenever RES goes low A transition can also be made to the reset state when the watchdog timer overflows The power down state also includes a watch mode subactive mode subsleep mode etc...

Page 81: ...instruction or current exception handling sequence High Low Trap instruction When TRAPA instruction is executed Exception handling starts when a trap TRAPA instruction is executed 2 Notes 1 Interrupt...

Page 82: ...SP CCR Normal Mode Advanced Mode 2 Notes 1 Ignored when returning 2 Normal mode is not available for this LSI Figure 2 16 Stack Structure after Exception Handling Examples 2 8 4 Program Execution Stat...

Page 83: ...ock input For details see section 4 Power Down State 1 Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit SSBY in the standby control reg...

Page 84: ...are used to access on chip memory and on chip supporting modules 2 9 2 On Chip Memory ROM RAM On chip memory is accessed in one state The data bus is 16 bits wide permitting both byte and word transfe...

Page 85: ...rnal address bus Internal read signal Internal data bus Internal write signal Internal data bus Bus cycle T1 Address Read access Write access Read data Write data T2 Figure 2 18 On Chip Supporting Mod...

Page 86: ...maximum of 16 Mbytes Mode 1 operation starts in single chip mode after reset release This LSI can only be used in mode 1 This means that the mode pins must be set at mode 1 Do not changes the inputs...

Page 87: ...ts cannot be modified and are always set at 0 Bit 0 Mode Select 0 MDS0 This bit indicates the value which reflects the input levels at mode pin MD0 the current operating mode Bit MDS0 corresponds to M...

Page 88: ...et source When the watchdog timer is used a reset can be generated by watchdog timer overflow as well as by external reset input XRST is a read only bit It is set to 1 by an external reset and cleared...

Page 89: ...Rev 2 0 11 00 page 62 of 1037 3 3 Operating Mode Descriptions 3 3 1 Mode 1 The CPU can access a 16 Mbyte address space in advanced mode...

Page 90: ...nal I O register On chip RAM 3kbytes Vector area On chip ROM 96 kbytes Internal I O register Internal I O register On chip RAM 3kbytes H 000000 H 000000 H 017FFF H FFD000 H FFD2FF H FFF3B0 H FFFFAF H...

Page 91: ...ternal I O register On chip RAM 3kbytes Vector area On chip ROM 128 kbytes Internal I O register Internal I O register On chip RAM 3kbytes H 000000 H 000000 H 01FFFF H FFD000 H FFD2FF H FFF3B0 H FFFFA...

Page 92: ...register On chip RAM 6 kbytes Vector area On chip ROM 192 kbytes Internal I O register Internal I O register On chip RAM 6 kbytes H 000000 H 000000 H 02FFFF H FFD000 H FFD2FF H FFE7B0 H FFFFAF H FFFF...

Page 93: ...66 of 1037 H8S 2194C Vector area On chip ROM 256 kbytes Internal I O register Internal I O register On chip RAM 6 kbytes H 000000 H 03FFFF H FFD000 H FFD2FF H FFE7B0 H FFFFAF H FFFFB0 H FFFFFF Figure...

Page 94: ...CPU on chip supporting modules and so on This LSI operating modes are as follows 1 High speed mode 2 Medium speed mode 3 Subactive mode 4 Sleep mode 5 Subsleep mode 6 Watch mode 7 Module stop mode 8 S...

Page 95: ...d reset Watchdog timer Functioning Functioning Functioning Functioning Halted retained Halted retained Halted retained Halted retained PSU Functioning Subclock operation Subclock operation Subclock op...

Page 96: ...NMI IRQ0 to 1 NMI IRQ0 to 1 Timer A interruption All interruption excluding servo system NMI IRQ0 to 5 Timer A interruption 1 2 3 4 Interrupt Interrupt SLEEP instruction SLEEP instruction e Note When...

Page 97: ...d medium speed 1 0 1 1 0 0 Standby High speed medium speed 1 1 0 1 1 1 0 0 Watch High speed medium speed 1 1 1 1 0 Watch Subactive 1 1 0 1 High speed medium speed 1 1 1 1 Subactive 0 0 0 1 0 0 1 1 Sub...

Page 98: ...summarizes these registers Table 4 3 Power Down State Registers Name Abbreviation R W Initial Value Address Standby control register SBYCR R W H 00 H FFEA Low power control register LPWRCR R W H 00 H...

Page 99: ...nsition to subsleep mode after execution of SLEEP instruction in subactive mode Initial value 1 Transition to standby mode subactive mode or watch mode after execution of SLEEP instruction in high spe...

Page 100: ...FLASH ROM version do not set the standby time to 16 states The standby time is 32 states when transited to medium speed mode 32 SCK1 1 SCK0 0 Bit 3 2 Reserved These bits cannot be modified and are alw...

Page 101: ...0 When a SLEEP instruction is executed in high speed mode or medium speed mode a transition is made to sleep mode standby mode or watch mode When a SLEEP instruction is executed in subactive mode a t...

Page 102: ...mode or watch mode After watch mode is cleared a transition is made to subactive mode Bit 5 Noise Elimination Sampling Frequency Select NESEL Selects the frequency at which the subclock w generated by...

Page 103: ...mode The operation mode to which the MCU is transited after SLEEP instruction execution is determined by the combination with other control bits than this bit For details see the description of Clock...

Page 104: ...MSTP1 R W 0 1 MSTP0 R W MSTPCRL Bit Initial value R W MSTPCR comprises two 8 bit readable writable registers that perform module stop mode control MSTPCR is initialized to H FFFF by a reset MSTRCRH a...

Page 105: ...is cleared at the end of the current bus cycle If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are cleared to 0 a transition is made to sleep mode When sleep...

Page 106: ...it PWM do not stop 4 4 2 Clearing Sleep Mode Sleep mode is cleared by any interrupt or with the 5 6 pin 1 Clearing with an Interrupt When an interrupt request signal is input sleep mode is cleared and...

Page 107: ...end of the bus cycle In module stop mode the internal states of modules other than the SCI1 A D converter Timer X1 and Servo circuit are retained After reset release all modules are in module stop mod...

Page 108: ...upt When an NMI 54 to 54 interrupt request signal is input clock oscillation starts and after the elapse of the time set in bits STS2 to STS0 in SYSCR stable clocks are supplied to the entire chip sta...

Page 109: ...68 states 3 3 4 1 0 1 1 65536 states 6 6 8 2 0 131072 states 13 1 16 4 0 1 262144 states 26 2 32 8 ms 1 1 16 states 1 1 6 2 0 s Recommended time setting Note Don t care 2 Using an External Clock Any v...

Page 110: ...equest signal is input watch mode is cleared and a transition is made to high speed mode or medium speed mode if the LSON bit in LPWRCR is cleared to 0 or to subactive mode if the LSON bit is set to 1...

Page 111: ...ports retain their states prior to the transition 4 8 2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt Timer A interrupt NMI pin or pin 54 to 54 or by means of the 5 6 pin 1 Clearing...

Page 112: ...ction or by means of the 5 6 pin 1 Clearing with a SLEEP Instruction When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1 the DTON bit in LPWRCR is cleared to 0 and the TMA3 bi...

Page 113: ...e to Subactive Mode If a SLEEP instruction is executed in high speed mode while the SSBY bit in SBYCR the LSON bit and DTON bit in LPWRCR and the TMA3 bit in TMA Timer A are all set to 1 a transition...

Page 114: ...after a low to high transition at the 5 6 pin or when the watchdog timer overflows Trace 1 Starts when execution of the current instruction or exception handling ends if the trace T bit is set to 1 In...

Page 115: ...and program execution starts from that address For a reset exception steps 2 and 3 above are carried out 5 1 3 Exception Sources and Vector Table The exception sources are classified as shown in figu...

Page 116: ...3 H 0034 to H 0037 14 H 0038 to H 003B Reserved for system use 15 H 003C to H 003F 0 16 H 0040 to H 0043 1 17 H 0044 to H 0047 Address trap 2 18 H 0048 to H 004B Internal interrupt IC 19 H 004C to H 0...

Page 117: ...set state when the 5 6 pin goes low To ensure that the chip is reset hold the 5 6 pin low during the oscillation stabilizing time of the clock oscillator when powering on To reset the chip during oper...

Page 118: ...of first program instruction 2 4 Figure 5 2 Reset Sequence Mode 1 5 2 3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer SP is initialized the PC and CCR...

Page 119: ...urce has a separate vector address NMI is the highest priority interrupt Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes and can assign i...

Page 120: ...a start address from a vector table entry corresponding to a vector number from 0 to 3 as specified in the instruction code Table 5 3 shows the status of CCR and EXR after execution of trap instructi...

Page 121: ...handling and interrupt exception handling CCR CCR PC 16 bits SP Note Ignored on return Interrupt control modes 0 and 1 Figure 5 4 1 Stack Status after Exception Handling Normal Mode Note Normal mode...

Page 122: ...the following instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 5 5 shows an example of what happens when...

Page 123: ...Rev 2 0 11 00 page 96 of 1037...

Page 124: ...tting interrupt priorities Three priority levels can be set for each module for all interrupts except NMI 3 Independent Vector Addresses All interrupt sources are assigned independent vector addresses...

Page 125: ...gend IEGR IENR IRQR ICR SYSCR IRQ edge select register IRQ enable register IRQ status register Interrupt control register System control register NMI input unit Interrupt request Vector number I UI IR...

Page 126: ...can be selected 6 1 4 Register Configuration Table 6 2 summarizes the registers of the interrupt controller Table 6 2 Interrupt Controller Registers Name Abbreviation R W Initial Value Address 1 Syst...

Page 127: ...TM0 These bits select one of two interrupt control modes for the interrupt controller The INTM1 bit must not be set to 1 Bit 5 Bit 4 INTM1 INTM0 Interrupt Control Mode Description 0 0 Interrupts are c...

Page 128: ...pt source Bit n ICRn Description 0 Corresponding interrupt source is control level 0 non priority Initial value 1 Corresponding interrupt source is control level 1 priority n 7 to 0 Table 6 3 Correspo...

Page 129: ...readable writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0 IENR is initialized to H 00 by a reset Bits 7 and 6 Reserved Do not write 1 to them Bits 5 to 0 IRQ5...

Page 130: ...Q5EG to IRQ1EG These bits select detected edge for interrupts IRQ5 to IRQ1 Bits 6 to 2 IRQnEG Description 0 Interrupt request generated at falling edge of 54Q pin input Initial value 1 Interrupt reque...

Page 131: ...Do not write 1 to them Bits 5 to 0 IRQ5 to IRQ0 Flags These bits indicate the status of IRQ5 to IRQ0 interrupt requests Bit n IRQnF Description 0 Clearing conditions Initial value Cleared by reading...

Page 132: ...as the P1n input output pin Initial value 1 P1n IRQn pin functions as the 54Q input pin N 5 to 0 The following is the notes on switching the pin function by PMR1 1 When the port is set as the input p...

Page 133: ...Q5 to IRQ0 Interrupts Interrupts IRQ5 to IRQ0 are requested by an input signal at pins 54 to 54 Interrupts IRQ5 to IRQ0 have the following features a Using IEGR it is possible to select whether an int...

Page 134: ...nF setting Internal IRQnF IRQn input pin Figure 6 3 Timing of IRQnF Setting The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 26 Upon detection of IRQ5 to IRQ0 interrupts the...

Page 135: ...the higher the priority Priorities among modules can be set by means of ICR The situation when two or more modules are set to the same priority and priorities within a module are fixed as shown in ta...

Page 136: ...RQ4 25 H 0064 to H 0067 IRQ5 External pin 26 H 0068 to H 006B ICRA1 27 H 006C to H 006F 28 H 0070 to H 0073 29 H 0074 to H 0077 30 H 0078 to H 007B 31 H 007C to H 007F 32 H 0080 to H 0083 Reserved 33...

Page 137: ...H 00D3 8 bit interval timer Watchdog timer 53 H 00D4 to H 00D7 ICRC5 CTL 54 H 00D8 to H 00DB Drum latch 2 speed 55 H 00DC to H 00DF Capstan latch 2 speed 56 H 00E0 to H 00E3 Drum latch 3 phase 57 H 0...

Page 138: ...oller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR the priorities set in ICR and the masking state indicated by the I and UI bits in the...

Page 139: ...t care 2 Default Priority Determination The priority is determined for the selected interrupt and a vector number is generated If the same value is set for ICR acceptance of multiple interrupts is ena...

Page 140: ...same control level setting are generated at the same time the interrupt request with the highest priority according to the priority system shown in table 6 4 is selected 3 The I bit is then reference...

Page 141: ...evel 1 interrupt I C I 0 Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No No No No No No Save PC and CCR I 1 Read vector address Branch to interrupt handling routine I C No No H S W 1 H S W 1 H S W 2...

Page 142: ...re set in ICRA ICRB ICRC and ICRD respectively i e IRQ2 interrupt is set to control level 1 and other interrupts to control level 0 the situation is as follows 1 When I 0 all interrupts are enabled Pr...

Page 143: ...d and other interrupt requests are held pending An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0 and is accepted if the I b...

Page 144: ...No I C No No H S W 1 H S W 1 H S W 2 H S W 2 Yes No Yes No Interrupt generated Address trap interrupt Control level 1 interrupt I 0 I 0 UI 0 Save PC and CCR I 1 UI 1 Read vector address Branch to inte...

Page 145: ...utine start address vector address contents Interrupt handling routine start address 13 10 12 First instruction of interrupt handling routine 2 4 6 8 10 12 13 9 11 14 3 5 7 9 11 13 Internal address bu...

Page 146: ...s until executing instruction ends 2 1 to 19 2 SI 3 PC CCR stack save 2 Sk 4 Vector fetch 2 SI 5 Instruction fetch 3 2 SI 6 Internal processing 4 2 Total using on chip memory 12 to 32 Notes 1 Two stat...

Page 147: ...be executed on completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the higher priority inte...

Page 148: ...I issued during the transfer is not accepted until the move is completed With the EEPMOV W instruction if an interrupt request is issued during the transfer interrupt exception handling starts at a br...

Page 149: ...Rev 2 0 11 00 page 122 of 1037...

Page 150: ...ata bus The CPU accesses both byte and word data in one state enabling faster instruction fetches and higher processing speed The flash memory versions of the H8S 2194 can be erased and programmed on...

Page 151: ...10 ms typ for simultaneous 32 byte programming equivalent to 300 s typ per byte and the erase time is 100 ms typ per block Reprogramming capability The flash memory can be reprogrammed up to 100 time...

Page 152: ...r 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Legend Internal address bus Internal data bus 16 bits STCR FWE pin Mode pin FLMCR2 EBR1 EBR2 Note These registers are...

Page 153: ...not programmed or erased Flash memory can be programmed and erased in boot mode user program mode and programmer mode Boot mode On board program mode User program mode User mode Reset state Programme...

Page 154: ...new application program beforehand in the host 2 Programming control program transfer When boot mode is entered the boot program in the LSI originally incorporated in the chip is started and the progr...

Page 155: ...ssment program that confirms that the FWE pin has been driven high and 2 the program that will transfer the programming erase control program from the flash memory to on chip RAM should be written int...

Page 156: ...y Erase erase verify Program program verify Note To be provided by the user in accordance with the recommended algorithm 4 Block Configuration The flash memory is divided into two 32 kbyte blocks two...

Page 157: ...table 7 3 In order to access these registers the FLSHE bit in STCR must be set to 1 Table 7 3 Flash Memory Registers Register Name Abbreviation R W Initial Value Address 5 Access Size Flash memory con...

Page 158: ...lly setting the E bit FLMCR1 is initialized by a reset in power down state excluding the medium speed mode module stop mode and sleep mode or when a low level is input to the FWE pin Its initial value...

Page 159: ...nd are always read as 0 Bit 3 Erase Verify EV Selects erase verify mode transition or clearing Do not set the SWE ESU PSU PV E or P bit at the same time Bit 3 EV Description 0 Erase verify mode cleare...

Page 160: ...value 1 Transition to erase mode Setting condition Setting is available when FWE 1 SWE 1 and ESU 1 are selected Bit 0 Program P Selects program mode transition or clearing Do not set the SWE PSU ESU E...

Page 161: ...memory programming or erasing When FLER is set to 1 flash memory goes to the error protection state Bit 7 FLER Description 0 Flash memory is operating normally Flash memory program erase protection er...

Page 162: ...for a transition to program mode Set this bit to 1 before setting the P bit to 1 in FLMCR1 Do not set the SWE ESU EV PV E or P bit at the same time Bit 0 PSU Description 0 Program setup cleared Initi...

Page 163: ...nd sleep mode when a low level is input to the FWE pin or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set When a bit in EBR1 or EBR2 is set the corresponding block can b...

Page 164: ...vidual modules If a module controlled by STCR is not used do not write 1 to the corresponding bit STCR is initialized to H 00 by a reset Bits 6 5 I 2 C Control IICX IICRST These bits control the opera...

Page 165: ...ach of these modes are shown in table 7 5 For a diagram of the transitions to the various flash memory modes see figure 7 3 Table 7 5 Setting On Board Programming Modes Mode Pin Mode Name FWE MD0 P12...

Page 166: ...ceived via the SCI1 is written into the programming control program area in on chip RAM After the transfer is completed control branches to the start address of the programming control program area an...

Page 167: ...mitted by host After bit rate adjustment transmits one H 00 data byte to host to indicate end of adjustment Upon receiving H 55 this LSI transmits one H AA data byte to host Host confirms normal recep...

Page 168: ...H 00 has been received normally and transmit one H 55 byte to the MCU If reception cannot be performed normally initiate boot mode again reset and repeat the above operations Depending on the host s...

Page 169: ...ramming control program transferred into RAM enters the execution state A stack area should be set up as required H FFEFB0 H FFF7B0 Programming control program area 1920 bytes Reserved area 128 bytes...

Page 170: ...s internal general registers are undefined at this time so these registers must be initialized immediately after branching to the programming control program In particular since the stack pointer SP i...

Page 171: ...shows the procedure for executing the program erase control program when transferred to on chip RAM Clear FWE FWE high Branch to flash memory application program Branch to program erase control progra...

Page 172: ...ice to voltage stress or sacrificing program data reliability Programming should be carried out 32 bytes at a time Table 29 9 in section 29 2 7 Flash Memory Characteristics lists wait time x y z and a...

Page 173: ...o the addresses to be read The dummy write should be executed after the elapse of s or more When the flash memory is read in this state verify data is read in 16 bit units the data at the latched addr...

Page 174: ...eprogramming should be performed Still in erased state no action 1 2 3 4 5 Write 32 byte data in RAM reprogram data area consecutively to flash memory Programming must be excuted in the erased state D...

Page 175: ...ase procedure 7 5 4 Erase Verify Mode In erase verify mode data is read after memory has been erased to check whether it has been correctly erased After the elapse of the erase time erase mode is exit...

Page 176: ...Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N NO NO NO NO YES YES YES YES Notes 1 2 3 4 5 Increment ad...

Page 177: ...ardware Protection Functions Item Description Program Erase FWE pin protection When a low level is input to the FWE pin FLMCR1 FLMCR2 EBR1 and EBR2 are initialized and the program erase protected stat...

Page 178: ...sition to program mode or erase mode See table 7 8 Table 7 8 Software Protection Functions Item Description Program Erase SWE bit protection Clearing the SWE bit to 0 in FLMCR1 sets the program erase...

Page 179: ...sh memory is read during programming erasing including a vector read or instruction fetch 2 Immediately after exception handling excluding a reset during programming erasing 3 When a SLEEP instruction...

Page 180: ...al boot mode sequence For these reasons in on board programming mode alone there are conditions for disabling interrupt as an exception to the general rule However this provision does not guarantee no...

Page 181: ...uto program mode auto erase mode and status read mode a status polling procedure is used and in status read mode detailed internal signals are output after execution of an auto program or auto erase o...

Page 182: ...rm the end of auto erasing 4 Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the FO6 signal In status read mode error i...

Page 183: ...de 1 n write X H 00 read RA Dout Auto program mode 129 write X H 40 write WA Din Auto erase mode 2 write X H 20 write X H 20 Status read mode 2 write X H 71 write X H 71 Notes 1 In auto program mode 1...

Page 184: ...consecutive reads can be performed 4 After power on memory read mode is entered Table 7 12 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit C...

Page 185: ...tnxtc 20 s hold time tceh 0 ns setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns rise time tr 30 ns fall time tf 30 ns CE ADDRESS DATA H XX OE WE XX...

Page 186: ...output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE ADDRESS DATA VIL VIL VIH OE WE tacc toh toh tacc ADDRESS STABLE ADDRESS STABLE DATA DATA Figure 7 1...

Page 187: ...will be flagged d Memory address transfer is performed in the second cycle figure 7 20 Do not perform transfer after the second cycle e Do not perform a command write during a programming operation f...

Page 188: ...tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms rise time tr 30 ns fall time tf 30 ns Write setup time tpns 100 ns Write end setup time tpnh 100...

Page 189: ...retained until the next command write Until the next command write is performed reading is possible by enabling and 2 Table 7 16 AC Characteristics in Auto Erase Mode Conditions VCC 5 0 V 10 VSS 0 V T...

Page 190: ...has occurred Use this mode when an abnormal end occurs in auto program mode or auto erase mode 2 The return code is retained until a command write for other than status read mode is performed Table 7...

Page 191: ...de Return Commands Pin Name FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0 Attribute Normal end identifica tion Command error Program ming error Erase error Program ming or erase count exceeded Effective address err...

Page 192: ...ating status in auto program or auto erase mode 2 The FO6 status polling flag indicates a normal or abnormal end in auto program or auto erase mode Table 7 19 Status Polling Output Truth Table Pin Nam...

Page 193: ...de and auto erase mode drive the FWE input pin low Don t care Don t care Figure 7 23 Oscillation Stabilization Time Boot Program Transfer Time and Power Supply Fall Sequence 7 8 10 Notes On Memory Pro...

Page 194: ...ried out when MCU operation is in a stable condition If MCU operation is not stable fix the FWE pin low and set the protection state The following points must be observed concerning FWE application an...

Page 195: ...7 Do Not Use Interrupts while Flash Memory is Being Programmed or Erased All interrupt requests including NMI should be disabled during FWE application to give priority to program erase operations 8...

Page 196: ...in table 7 21 is read in the mask ROM version an undefined value will be returned Therefore if application software developed on the F ZTAT version is switched to a mask ROM version product it must b...

Page 197: ...Rev 2 0 11 00 page 170 of 1037...

Page 198: ...U accesses both byte and word data in one state enabling faster instruction fetches and higher processing speed The flash memory versions of the H8S 2194C can be erased and programmed on board as well...

Page 199: ...10 ms typ for simultaneous 32 byte programming equivalent to 300 s typ per byte and the erase time is 100 ms typ per block Reprogramming capability The flash memory can be reprogrammed up to 100 time...

Page 200: ...r 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Legend Internal address bus Internal data bus 16 bits STCR FWE pin Mode pin FLMCR2 EBR1 EBR2 Note These registers are...

Page 201: ...not programmed or erased Flash memory can be programmed and erased in boot mode user program mode and programmer mode Boot mode On board program mode User program mode User mode Reset state Programme...

Page 202: ...new application program beforehand in the host 2 Programming control program transfer When boot mode is entered the boot program in the LSI originally incorporated in the chip is started and the progr...

Page 203: ...ssment program that confirms that the FWE pin has been driven high and 2 the program that will transfer the programming erase control program from the flash memory to on chip RAM should be written int...

Page 204: ...Program program verify Note To be provided by the user in accordance with the recommended algorithm 4 Block Configuration The flash memory is divided into six 32 kbyte blocks two 8 kbyte blocks one 16...

Page 205: ...e shown in table 8 3 In order to access these registers the FLSHE bit in STCR must be set to 1 Table 8 3 Flash Memory Registers Register Name Abbreviation R W Initial Value Address 5 Flash memory cont...

Page 206: ...mode for addresses H 00000 to H 1FFFF is entered by setting SWE to 1 while FWE is 1 then setting the ESU1 bit and finally setting the E1 bit FLMCR1 is initialized by a reset in power down state exclu...

Page 207: ...e same time Bit 5 ESU1 Description 0 Erase setup cleared Initial value 1 Erase setup Setting condition When FWE 1 and SWE 1 Bit 4 Program Setup Bit 1 PSU1 Prepares erase mode transition for addresses...

Page 208: ...Selects erase mode transition or clearing Do not set the SWE ESU1 PSU1 EV1 PV1 or P1 bit at the same time Bit 1 E1 Description 0 Erase mode cleared Initial value 1 Transition to erase mode Setting co...

Page 209: ...e and sleep mode when a low level is input to the FWE pin or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set However FLER is initialized only by a reset Writes to the ES...

Page 210: ...ime Bit 4 PSU2 Description 0 Program setup cleared Initial value 1 Program setup Setting condition When FWE 1 and SWE 1 Bit 3 Erase Verify 2 EV2 Selects erase verify mode transition or clearing for ad...

Page 211: ...ion 0 Erase mode cleared Initial value 1 Transition to erase mode Setting condition When FWE 1 SWE 1 and ESU2 1 Bit 0 Program 2 P2 Selects program mode transition or clearing for addresses H 20000 to...

Page 212: ...it in EBR1 or EBR2 more than one bit cannot be set The flash memory block configuration is shown in table 8 3 8 3 4 Erase Block Registers 2 EBR2 7 EB7 0 R W 6 EB6 0 R W 5 EB5 0 R W 4 EB4 0 R W 3 EB3 0...

Page 213: ...H 000BFF EB3 1 kbyte H 000C00 to H 000FFF EB4 28 kbytes H 001000 to H 007FFF EB5 16 kbytes H 008000 to H 00BFFF EB6 8 kbytes H 00C000 to H 00DFFF EB7 8 kbytes H 00E000 to H 00FFFF EB8 32 kbytes H 010...

Page 214: ...idual modules If a module controlled by STCR is not used do not write 1 to the corresponding bit STCR is initialized to H 00 by a reset Bits 6 to 5 I 2 C Control IICX IICRST These bits control the ope...

Page 215: ...ach of these modes are shown in table 8 5 For a diagram of the transitions to the various flash memory modes see figure 8 3 Table 8 5 Setting On Board Programming Modes Mode Pin Mode Name FWE MD0 P12...

Page 216: ...ceived via the SCI1 is written into the programming control program area in on chip RAM After the transfer is completed control branches to the start address of the programming control program area an...

Page 217: ...mitted by host After bit rate adjustment transmits one H 00 data byte to host to indicate end of adjustment Upon receiving H 55 this LSI transmits one H AA data byte to host Host confirms normal recep...

Page 218: ...H 00 has been received normally and transmit one H 55 byte to the MCU If reception cannot be performed normally initiate boot mode again reset and repeat the above operations Depending on the host s...

Page 219: ...to the execution state in boot mode for the programming control program transferred to RAM H FFE7B0 H FFF3AF Programming control program area 2944 bytes Reserved area 128 bytes H FFFFAF H FFFF2F Boot...

Page 220: ...s internal general registers are undefined at this time so these registers must be initialized immediately after branching to the programming control program In particular since the stack pointer SP i...

Page 221: ...the procedure for executing the program erase control program when transferred to on chip RAM Clear FWE FWE high Branch to flash memory application program Branch to program erase control program in R...

Page 222: ...ammed at the same time 8 5 1 Program Mode n 1 for addresses H 0000 to H 1FFFF and n 2 for addresses H 20000 to H 3FFFF Follow the procedure shown in the program program verify flowchart in figure 8 12...

Page 223: ...dog timer is cleared after the elapse of s or more and the operating mode is switched to program verify mode by setting the PVn bit in FLMCRn Before reading in program verify mode a dummy write of H F...

Page 224: ...leted Programming incomplete reprogramming should be performed Still in erased state no action 1 2 3 4 5 Write 32 byte data in RAM reprogram data area consecutively to flash memory Programming must be...

Page 225: ...rase procedure 8 5 4 Erase Verify Mode n 1 for addresses H 00000 to H 1FFFF and n 2 for address H 20000 to H 3FFFF In erase verify mode data is read after memory has been erased to check whether it ha...

Page 226: ...s Clear EV bit in FLMCR1 or FLMCR2 Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N NO NO NO NO YES YES Y...

Page 227: ...cription Program Erase FWE pin protection When a low level is input to the FWE pin FLMCR1 FLMCR2 EBR1 and EBR2 are initialized and the program erase protected state is entered Yes Yes Reset standby pr...

Page 228: ...ister 2 FLMCR2 does not cause a transition to program mode or erase mode See table 8 8 Table 8 8 Software Protection Functions Item Description Program Erase SWE bit protection Clearing the SWE bit to...

Page 229: ...When flash memory is read during programming erasing including a vector read or instruction fetch 2 Immediately after exception handling excluding a reset during programming erasing 3 When a SLEEP in...

Page 230: ...l boot mode sequence For these reasons in on board programming mode alone there are conditions for disabling interrupt as an exception to the general rule However this provision does not guarantee nor...

Page 231: ...uto program mode auto erase mode and status read mode a status polling procedure is used and in status read mode detailed internal signals are output after execution of an auto program or auto erase o...

Page 232: ...rm the end of auto erasing 4 Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the FO6 signal In status read mode error i...

Page 233: ...de 1 n write X H 00 read RA Dout Auto program mode 129 write X H 40 write WA Din Auto erase mode 2 write X H 20 write X H 20 Status read mode 2 write X H 71 write X H 71 Notes 1 In auto program mode 1...

Page 234: ...consecutive reads can be performed 4 After power on memory read mode is entered Table 8 12 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit C...

Page 235: ...tnxtc 20 s hold time tceh 0 ns setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns rise time tr 30 ns fall time tf 30 ns CE ADDRESS DATA H XX OE WE XX...

Page 236: ...output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE ADDRESS DATA VIL VIL VIH OE WE tacc toh toh tacc ADDRESS STABLE ADDRESS STABLE DATA DATA Figure 8 1...

Page 237: ...will be flagged d Memory address transfer is performed in the second cycle figure 8 20 Do not perform transfer after the second cycle e Do not perform a command write during a programming operation f...

Page 238: ...tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms rise time tr 30 ns fall time tf 30 ns Write setup time tpns 100 ns Write end setup time tpnh 100...

Page 239: ...retained until the next command write Until the next command write is performed reading is possible by enabling and 2 Table 8 16 AC Characteristics in Auto Erase Mode Conditions VCC 5 0 V 10 VSS 0 V T...

Page 240: ...has occurred Use this mode when an abnormal end occurs in auto program mode or auto erase mode 2 The return code is retained until a command write for other than status read mode is performed Table 8...

Page 241: ...de Return Commands Pin Name FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0 Attribute Normal end identifica tion Command error Program ming error Erase error Program ming or erase count exceeded Effective address err...

Page 242: ...ating status in auto program or auto erase mode 2 The FO6 status polling flag indicates a normal or abnormal end in auto program or auto erase mode Table 8 19 Status Polling Output Truth Table Pin Nam...

Page 243: ...de and auto erase mode drive the FWE input pin low Don t care Don t care Figure 8 23 Oscillation Stabilization Time Boot Program Transfer Time and Power Supply Fall Sequence 8 8 10 Notes On Memory Pro...

Page 244: ...in a stable condition If MCU operation is not stable fix the FWE pin low and set the protection state The following points must be observed concerning FWE application and disconnection to prevent uni...

Page 245: ...erasing 7 Do Not Use Interrupts while Flash Memory is Being Programmed or Erased All interrupt requests including NMI should be disabled during FWE application to give priority to program erase operat...

Page 246: ...in table 8 21 is read in the mask ROM version an undefined value will be returned Therefore if application software developed on the F ZTAT version is switched to a mask ROM version product it must b...

Page 247: ...Rev 2 0 11 00 page 220 of 1037...

Page 248: ...AM is connected to the CPU by a 16 bit data bus enabling both byte data and word data to be accessed in one state This makes it possible to perform fast word data transfer 9 1 1 Block Diagram Figure 9...

Page 249: ...Rev 2 0 11 00 page 222 of 1037...

Page 250: ...System clock oscillator Duty adjustment circuit Clock selection circuit Medium speed clock divider Subclock oscillator Subclock division circuit OSC1 OSC2 X1 X2 16 32 64 w 2 w 4 w 8 SUB or SUB Timer...

Page 251: ...own mode control Only bits 0 and 1 are described here For a description of the other bits see section 4 2 1 Standby Register SBYCR SBYCR is initialized to H 00 by a reset Bits 1 and 0 System Clock Sel...

Page 252: ...control Only bit 1 and 0 is described here For a description of the other bits see section 4 2 2 Low Power Control Register LPWRCR LPWRCR is initialized to H 00 by a reset Bits 1 and 0 Subactive Mode...

Page 253: ...rystal should be used OSC1 OSC2 Rf CL2 CL1 CL1 CL2 10 to 22pF Rf 1M 20 Figure 10 2 Connection of Crystal Resonator Example 2 Crystal Resonator Figure 10 3 shows the equivalent circuit of the crystal r...

Page 254: ...uld be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation See figure 10 4 When designing the board place the crystal resonator and its load capacito...

Page 255: ...e OSC2 pin is left open make sure that stray capacitance is no more than 10 pF In example b make sure that the external clock is held high in standby mode subactive mode subsleep mode and watch mode O...

Page 256: ...time tCPf 10 ns Figure 10 6 tCPH tCPL tCPr tCPf OSC1 Figure 10 6 External Clock Input Timing Table 10 4 shows the external clock output settling delay time and figure 10 7 shows the external clock ou...

Page 257: ...0 V to 5 5 V VSS AVSS 0 V Item Symbol Min Max Unit Notes External clock output settling delay time tDEXT 500 s Figure 10 7 Note tDEXT includes 20 tCYC of 5 6 pulse width tRESW tDEXT RES Internal OSC1...

Page 258: ...llator to generate the system clock 10 5 Medium Speed Clock Divider The medium speed divider divides the system clock to generate 16 32 and 64 clocks 10 6 Bus Master Clock Selection Circuit The bus ma...

Page 259: ...ions on connecting see section 10 3 1 3 Note on Board Design The subclock input conditions are shown in figure 10 10 X1 X2 C2 C1 C1 C2 15 pF Typ Figure 10 8 Connecting a 32 768 kHz Crystal Resonator E...

Page 260: ...X2 pin should remain open as connection example of figure 10 10 X1 X2 Open External clock input Figure 10 10 Connection Example When Inputting External Clock 10 7 3 When Subclock is not Needed Connect...

Page 261: ...in subactive mode subsleep mode or watch mode 10 9 Notes on the Resonator Resonator characteristics are closely related to the user board design Perform appropriate assessment of resonator connection...

Page 262: ...et to the peripheral function are read the results are as given in items 1 and 2 according to the PCR value 2 Processing Input Pins The general input port or general I O port is gated by read signals...

Page 263: ...Timer J buzzer output P35 PWM3 to P32 PWM0 8 bit PWM output P31 STRB SCI2 strobe output Port 3 P37 to P30 I O ports Built in MOS pull up transistors P30 6 SCI2 chip select input PMR3 P47 None P46 FTO...

Page 264: ...a MOS pull up transistor When the pin whose peripheral function is used both as an alternative function is set to the alternative output function the MOS pull up transistor is turned off When the pin...

Page 265: ...egister 0 PMR0 Table 11 2 Port 0 Configuration Port Function Alternative Function P07 standard input port AN7 analog input channel P06 standard input port AN6 analog input channel P05 standard input p...

Page 266: ...PMR04 PMR03 PMR02 PMR01 PMR00 PMR07 PMR06 PMR05 Bit Initial value R W Port mode register 0 PMR0 controls switching of each pin function of port 0 The switching is specified in a unit of bit PMR0 is an...

Page 267: ...ad only register When PDR0 is reset its values become undefined 11 2 3 Pin Functions This section describes the pin functions of port 0 and their selection methods 1 P07 AN7 to P00 AN0 P07 AN7 to P00...

Page 268: ...rd I O port input capture input P15 standard I O port 54 external interrupt request input P14 standard I O port 54 external interrupt request input P13 standard I O port 54 external interrupt request...

Page 269: ...of P16 and P15 54 to P10 54 are switched by PMR1 they are incorrectly recognized as edge detection according to the state of a pin signal and a detection signal may be generated To prevent this perfor...

Page 270: ...n functions as a P1n I O pin Initial value 1 The P1n 54Q pin functions as an 54Q input pin n 5 to 0 2 Port Control Register 1 PCR1 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 0 7 0 W W W W 6 PCR14 PCR13 PCR12 PCR...

Page 271: ...lized to H 00 4 MOS Pull Up Select Register 1 PUR1 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 0 7 0 R W R W R W R W 6 PUR14 PUR13 PUR12 PUR11 PUR10 PUR17 PUR16 PUR15 Bit Initial value R W MOS pull up sel...

Page 272: ...R1 PMR16 PCR16 NC on off Pin Function 0 P16 input pin 0 1 P16 output pin 0 Noise cancel invalid 1 1 input pin Noise cancel valid 3 P15 54 to P10 54 P15 54 to P10 54 are switched as shown below accordi...

Page 273: ...ndby Watch Subactive Subsleep P17 TMOW P16 P15 54 to P10 54 High impedance Operation Holding High impedance High impedance Operation Holding Note If the input pin and 54 to 54 input pins are set the p...

Page 274: ...n P27 standard I O port SCK2 SCI2 clock I O P26 standard I O port SO2 SCI2 transmit data output P25 standard I O port SI2 SCI2 receive data input P24 standard I O port SCL I 2 C bus interface clock I...

Page 275: ...are set the pin level need be set to the high or low level regardless of the active mode and low power consumption mode Note that the pin level must not reach an intermediate level Bit 7 P27 SCK2 Pin...

Page 276: ...tput Initial value 1 The P26 SO2 pin functions as NMOS open drain output 2 Port Control Register 2 PCR2 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 0 7 0 W W W W 6 PCR24 PCR23 PCR22 PCR21 PCR20 PCR27 PCR26 PCR25...

Page 277: ...zed to H 00 4 MOS Pull Up Select Register 2 PUR2 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 0 7 0 R W R W R W R W 6 PUR24 PUR23 PUR22 PUR21 PUR20 PUR27 PUR26 PUR25 Bit Initial value R W MOS pull up selec...

Page 278: ...0 Pin Function 0 P27 input pin 0 1 P27 output pin Other than 111 SCK2 output pin 1 111 SCK2 input pin Note Don t care 2 P26 SO2 P26 SO2 is switched as shown below according to the PMR26 bit in PMR2 an...

Page 279: ...CE bit in the I 2 C bus control register and the PCR23 bit in PCR2 ICE PCR23 Pin Function 0 P23 input pin 0 1 P23 output pin 1 SDA I O pin Note Don t care 6 P22 SCK1 P22 SCK1 is switched as shown belo...

Page 280: ...es Table 11 10 shows the port 2 pin states in each operation mode Table 11 10 Port 2 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P27 SCK2 P26 SO2 P25 SI2 P24 SCL P23 SDA P22 SC...

Page 281: ...timer J timer output P36 standard I O port BUZZ timer J buzzer output P35 standard I O port PWM3 8 bit PWM output P34 standard I O port PWM2 8 bit PWM output P33 standard I O port PWM1 8 bit PWM outp...

Page 282: ...for the timer J output timer Bit 7 PMR37 Description 0 The P37 TMO pin functions as a P37 I O pin Initial value 1 The P37 TMO pin functions as a TMO output pin Note If the TMO pin is used for remote c...

Page 283: ...2 m 3 to 0 Bit 1 P31 STRB Pin Switching PMR31 PMR31 sets whether the P31 STRB pin is used as a P31 I O pin or an STRB pin for the SCI2 strobe output Bit 1 PMR31 Description 0 The P31 STRB pin function...

Page 284: ...only register When PCR3 is read 1 is read When reset PCR3 is initialized to H 00 Bit n PCR3n Description 0 The P3n pin functions as an input pin Initial value 1 The P3n pin functions as an output pin...

Page 285: ...et to 1 output the corresponding bit of PUR3 becomes invalid and the MOS pull up transistor is turned off PUR3 is an 8 bit read write enable register When reset PUR3 is initialized to H 00 Bit n PCR3n...

Page 286: ...MR3 and the PCR3n bit in PCR3 PMR3n PCR3n Pin Function 0 P3n input pin 0 1 P3n output pin 1 PWMm output pin n 5 to 2 m 3 to 0 Note Don t care 4 P31 STRB P31 STRB is switched as shown below according t...

Page 287: ...andby Watch Subactive Subsleep P37 TMO P36 BUZZ P35 PWM3 to P32 PWM0 P31 STRB P30 6 High impedance Operation Holding High impedance High impedance Operation Holding Note If the 6 input pin is set the...

Page 288: ...andard I O port FTOB timer X1 output compare output P45 standard I O port FTOA timer X1 output compare output P44 standard I O port FTID timer X1 input capture input P43 standard I O port FTIC timer X...

Page 289: ...o the high or low level regardless of the active mode and low power consumption mode Note that the pin level must not reach an intermediate level excluding reset standby and watch modes Because the FT...

Page 290: ...only register When PCR4 is read 1 is read When reset PCR4 is initialized to H 00 Bit n PCR4n Description 0 The P4n pin functions as an input pin Initial value 1 The P4n pin functions as an output pin...

Page 291: ...below according to the PCR46 bit in PCR4 and the OEB bit in TOCR OEB PCR46 Pin Function 0 P46 input pin 0 1 P46 output pin 1 FTOB output pin Note Don t care 3 P45 FTOA P45 FTOA is switched as shown be...

Page 292: ...he PCR42 bit in PCR4 PCR42 Pin Function 0 P42 input pin 1 P42 output pin FTIB input pin 7 P41 FTIA P41 FTIA is switched as shown below according to the PCR41 bit in PCR4 PCR41 Pin Function 0 P41 input...

Page 293: ...FTOA P44 FTID P43 FTIC P42 FTIB P41 FTIA P40 PWM14 High impedance Operation Holding High impedance High impedance Operation Holding Note Because the FTIA FTIB FTIC and FTID inputs always function the...

Page 294: ...PCR5 Table 11 17 Port 5 Configuration Port Function Alternative Function P53 standard I O port TRIG realtime output port trigger input P52 standard I O port TMBI timer B event input P51 standard I O...

Page 295: ...ess of the active mode and low power consumption mode Note that the pin level must not reach an intermediate level Bits 7 to 4 Reserved Bits When the bits are read 1 is always read The write operation...

Page 296: ...PCR51 W PCR50 0 W PCR52 0 W PCR53 Bit Initial value R W Port control register 5 PCR5 controls the I Os of pins P53 to P50 of port 5 in a unit of bit When PCR5 is set to 1 the corresponding P53 to P50...

Page 297: ...a register 5 PDR5 stores the data for the pins P53 to P50 of port 5 When PCR5 is 1 output the PDR5 values are directly read if port 5 is read Accordingly the pin states are not affected When PCR5 is 0...

Page 298: ...P52 TMBI is switched as shown below according to the PMR52 bit in PMR5 and the PCR52 bit in PCR5 PMR52 PCR52 Pin Function 0 P52 input pin 0 1 P52 output pin 1 TMBI input pin Note Don t care 3 P51 P51...

Page 299: ...by Watch Subactive Subsleep P53 TRIG P52 TMBI P51 P50 57 High impedance Operation Holding High impedance High impedance Operation Holding Note If the TRIG TMBI and 75 input pins are set the alternativ...

Page 300: ...ntaneously switch the output data by an external or internal trigger input Table 11 20 Port 6 Configuration Port Function Alternative Function P67 standard I O port RP7 realtime output port pin P66 st...

Page 301: ...ster slave 6 PDRS6 Byte H 00 Note Lower 16 bits of the address 1 Port Mode Register 6 PMR6 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 6 0 7 PMR64 PMR63 PMR62 PMR61 PMR60 0 R W PMR67 R W R W R W PMR66 PMR...

Page 302: ...to H 00 PMR6 PCR6 Bit n Bit n PMR6n PCR6n Description 0 The P6n RPn pin functions as a P6n general I O input pin Initial value 0 1 The P6n RPn pin functions as a P6n general output pin 1 The P6n RPn...

Page 303: ...sets whether the external trigger TRIG pin input or the internal trigger HSW is used as an trigger input for the realtime output in a unit of bit For the internal trigger HSW see section 28 4 HSW Timi...

Page 304: ...internal trigger input for the realtime output Bit 1 Bit 0 RTPEGR1 RTPEGR0 Description 0 Inhibits a trigger input Initial value 0 1 Selects the rising edge of a trigger input 0 Selects the falling ed...

Page 305: ...DRS6 RTPSR RTPEGR HSW TRIG Port mode register 6 Port control register 6 Port data register 6 Port control register slave 6 Port data register slave 6 Realtime output trigger select register Realtime o...

Page 306: ...neral I O port PMR6 0 When PMR6 is 0 it operates as a general I O port When data is written to PDR6 the same data is also written to PDRS6 Accordingly because both PDR6 and PDRS6 and both PCR6 and PCR...

Page 307: ...tion P77 standard I O port PPG7 HSW timing output P76 standard I O port PPG6 HSW timing output P75 standard I O port PPG5 HSW timing output P74 standard I O port PPG4 HSW timing output P73 standard I...

Page 308: ...The P7n PPGn pin functions as a P7n I O pin Initial value 1 The P7n PPGn pin functions as a PPGn output pin n 7 to 0 2 Port Control Register 7 PCR7 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 6 0 7 PCR74 PCR73 PC...

Page 309: ...read write enable register When reset PDR7 is initialized to H 00 11 9 3 Pin Functions This section describes the port 7 pin functions and their selection methods 1 P77 PPG7 to P70 PPG0 P77 PPG7 to P7...

Page 310: ...ion Port Function Alternative Function P87 high current I O port None P86 high current I O port None P85 high current I O port None P84 high current I O port None P83 high current I O port SV2 servo m...

Page 311: ...e level Bits 7 to 4 Reserved Bits When the bits are read 1 is always read The write operation is valid Bit 3 P83 SV2 Pin Switching PMR83 PMR83 sets whether the P83 SV2 pin is used as a P83 I O pin or...

Page 312: ...in Initial value 1 The P80 EXTTRG pin functions as an EXTTRG input pin 2 Port Control Register 8 PCR8 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 6 0 7 PCR84 PCR83 PCR82 PCR81 PCR80 0 W PCR87 W W W PCR86 PCR85 Bi...

Page 313: ...is 0 input the pin states are read if port 8 is read PDR8 is an 8 bit read write enable register When reset PDR8 is initialized to H 00 11 10 3 Pin Functions This section describes the port 8 pin func...

Page 314: ...on t care 4 P81 EXCAP P81 EXCAP is switched as shown below according to the PMR81 bit in PRM8 and the PCR81 bit in PCR8 PMR81 PCR81 Pin Function 0 P81 input pin 0 1 P81 output pin 1 EXCAP input pin No...

Page 315: ...ch Subactive Subsleep P87 to P84 P83 SV2 P83 SV1 P81 EXCAP P80 EXTTRG High impedance Operation Holding High impedance High impedance Operation Holding Note If the EXCAP and EXTTRG input pins are set t...

Page 316: ...or 12 1 1 Features Features of the Timer A are as follows Choices of eight different types of internal clocks 16384 8192 4096 1024 512 256 64 and 16 are available for your selection Four different ove...

Page 317: ...output w 128 is working as the input clock to the TCA Prescaler S PSS Interrupting circuit Prescaler unit Prescaler W PSW TCA 1 4 TMA Interrupt requests Internal data bus 8 64 128 256 Figure 12 1 Blo...

Page 318: ...status flag indicating the fact that the TCA is overflowing H FF H 00 Bit 7 TMAOV Description 0 Clearing conditions Initial value When 0 is written to the TMAOV flag after reading the TMAOV flag unde...

Page 319: ...k Selection TMA2 to TMA0 These bits work to select the clock to input to the TCA In combination with the TMA3 bit the choices are as follows Bit 3 Bit 2 Bit 1 Bit 0 TMA3 TMA2 TMA1 TMA0 Prescaler divis...

Page 320: ...RH 6 1 MSTP14 R W 5 1 MSTP13 R W 4 1 MSTP12 R W 3 1 MSTP11 R W 2 1 MSTP10 R W 1 1 MSTP9 R W 0 1 MSTP8 R W 7 1 MSTP7 R W 6 1 MSTP6 R W 5 1 MSTP5 R W 4 1 MSTP4 R W 3 1 MSTP3 R W 2 1 MSTP2 R W 1 1 MSTP1...

Page 321: ...ccurs When overflowing occurs the reading of the TCA returns to H 00 before resuming counting up Consequently it works as the interval timer to produce overflow outputs periodically at every 256 input...

Page 322: ...1024 512 128 32 and 8 or selection of external clock are possible When the counter overflows a interrupt request will be issued 13 1 2 Block Diagram Figure 13 1 shows a block diagram of the Timer B L...

Page 323: ...ration Table 13 2 shows the register configuration of the Timer B The TCB and TLB are being allocated to the same address Reading or writing determines the accessing register Table 13 2 Register Confi...

Page 324: ...select the input clock When reset the TMB is initialized to H 18 Bit 7 Selecting the Auto Reloading Function TMB17 This bit works to select the auto reloading function of the Timer B Bit 7 TMB17 Desc...

Page 325: ...to select the clock to input to the TCB Selection of the rising edge or the falling edge is workable with the external event inputs Bit 2 Bit 1 Bit 0 TMB12 TMB11 TMB10 Descriptions 0 0 0 Internal clo...

Page 326: ...n reset the TCB is initialized to H 00 13 2 3 Timer Load Register B TLB 0 0 1 0 W 2 0 W 3 4 5 0 6 0 7 W W TLB15 0 W TLB14 0 W TLB13 W TLB16 0 W TLB17 TLB12 TLB11 TLB10 Bit Initial value R W The TLB is...

Page 327: ...51 Description 0 Detects the falling edge of the event inputs to the Timer B Initial value 1 Detects the rising edge of the event inputs to the Timer B 13 2 5 Module Stop Control Register MSTPCR 7 1 M...

Page 328: ...37 Bit 6 Module Stop MSTP14 This bit works to designate the module stop mode for the Timer B MSTPCRH Bit 6 MSTP14 Description 0 Cancels the module stop mode of the Timer B 1 Sets the module stop mode...

Page 329: ...ue which has been set to the TLB will be loaded to the TCB simultaneously 13 3 2 Operation as the Auto Reload Timer When the TMB17 of the TMB is set to 1 the Timer B works as an 8 bit auto reload time...

Page 330: ...bit reloading timers Among the two one is capable to make timer outputs b Twin 8 bit event counters Capable to make reloading c 8 bit event counter Capable to make reloading 8 bit reload timer d 16 bi...

Page 331: ...selection 8 16 T R 8 bit 16 bit operation changeover Timer output Remote controller output changeover Internal data bus Edge detection Toggle T R Down counter 8 bit BUSS Output Control Monitor Output...

Page 332: ...TLK are being allocated to the same address respectively Reading or writing determines the accessing register Table 14 2 Register Configuration Name Abbrev R W Size Initial Value Address 2 Timer mode...

Page 333: ...ecting the Inputting Clock to the TMJ 1 PS11 and PS10 These bits work to select the clock to input to the TMJ 1 Selection of the rising edge or the falling edge is workable for counting by use of an e...

Page 334: ...ring remote controlled operation the ST bit will be cleared to 0 When resuming operation after returning to the active mode write 1 Bit 5 ST Description 0 Works to stop clock signal supply to the TMJ...

Page 335: ...register IEGR See section 6 2 4 Edge Select Register IEGR for more information 2 Don t care 3 Available only in the H8S 2194C series Bit 1 TMJ 2 Toggle Flag TGL This flag indicates the toggled status...

Page 336: ...H FF Consequently writing into the reloading registers TLJ an TLK should be conducted after finishing settings with the TMJ Under the remote controlling mode although the TLJ and the TLK will not be...

Page 337: ...an 8 bit read write register When reset the TMJC is initialized to H 09 Bits 7 and 6 Selecting the Buzzer Output BUZZ1 or BUZZ0 This bit works to select if using the buzzer outputs as the output sign...

Page 338: ...of the Timer A will be output 50 duty When the prescaler is being used with the Timer A 1Hz outputs are available Bit 5 Bit 4 MON1 MON0 Description 0 PB or REC CTL Initial value 0 1 DVCTL 1 Outputs T...

Page 339: ...mer J The TMJS is an 8 bit read write register When reset the TMJS is initialized to H 3F Bit 7 TMJ2I Interrupt Requesting Flag TMJ2I This is the TMJ2I interrupt requesting flag This flag is set when...

Page 340: ...it the TMJ1I bit of the TMJS will be set to 1 The TCJ and TLJ are being allocated to the same address When reset the TCJ is initialized to H FF 14 2 5 Timer Counter K TCK 0 1 1 1 R 2 1 R 3 1 4 1 R 5 1...

Page 341: ...tten into the TLJ The TLJ and TCJ are being allocated to the same address When reset the TLJ is initialized to H FF 14 2 7 Timer Load Register K TLK 0 1 1 1 W 2 1 W 3 1 4 1 W 5 1 6 1 7 W W W TLR25 W T...

Page 342: ...MSTPCR are 8 bit read write twin registers which work to control the module stop mode When the MSTP13 bit is set to 1 the Timer J stops its operation at the ending point of the bus cycle to shift to t...

Page 343: ...e written into the 16 bit counter Also when the 16 bit counter underflows the data of the 16 bit reloading register will be reloaded into the counter Even when they are making a 16 bit operation the T...

Page 344: ...when a writing is made to the burst space duration register while remote controlled data transmission is being made reloading operation will not be made until an underflow signal is issued The TMJ 2...

Page 345: ...Rev 2 0 11 00 page 318 of 1037 TMJ 1 UDF TMO BUZZ TMJ 2 UDF REMOout TMO Remote controlled data transmission output Figure 14 3 Timer Output Timing...

Page 346: ...a cycle of the inputting clock After that operations can be continued by interrupts Similarly pay attention to the control works when ending remote controlled data transmission Exemple 1 Set the burst...

Page 347: ...Rev 2 0 11 00 page 320 of 1037...

Page 348: ...CFG2 CFG division signal 2 PB and REC CTL control pulses are available for your selection In case the PB CTL is not available such as when reproducing un recorded tapes tape count can be made by the D...

Page 349: ...REC CTL Control pluses necessary when making reproduction and storage LMR Timer L mode register LTC Linear time counter RCR Reload compare match register OVF Overflow UDF Underflow LMR LTC RCR Compara...

Page 350: ...re patch register RCR are being allocated to the same address Reading or writing determines the accessing register Table 15 1 Register Configuration Name Abbrev R W Size Initial Value Address Timer L...

Page 351: ...erflow of the LTC or occurrence of compare match clear Bit 7 LMIF Description 0 Clearing conditions Initial value When 0 is written after reading 1 1 Setting conditions When the LTC overflows underflo...

Page 352: ...LTC and counting down starts from that value When the LTC underflows the value of the RCR will be reloaded to the LTC Also when the LTC underflows a interrupt request will be issued Auto reload timer...

Page 353: ...RCR1 RCR0 Bit Initial value R W The reload compare match register RCR is an 8 bit write only register When the Timer L is being controlled to the up counting function when a compare match value is set...

Page 354: ...MSTPCR are 8 bit read write twin registers which work to control the module stop mode When the MSTP12 bit is set to 1 the Timer L stops its operation at the ending point of the bus cycle to shift to t...

Page 355: ...mode Respective operation modes and operation methods will be explained below 15 3 1 Compare Match Clear Operation When the LMR3 bit of the LMR is cleared to 0 the Timer L will be controlled to the up...

Page 356: ...1 00 page 329 of 1037 LTC RCR N H 00 N 1 N Interrupt request Count up signal Compare match clear signal PB CTL Figure 15 3 Compare Match Clearing Timing Chart In case the rising edge of the PB CTL is...

Page 357: ...Rev 2 0 11 00 page 330 of 1037...

Page 358: ...ng three units of timers it can be used for the following applications 1 Applications making use of the functions of three units of reloading timers 2 For identification of the VCR mode 3 For reel con...

Page 359: ...P SLM SLW CAPF Capture register 8 bits Down counter 8 bits Reloading register 8 bits Acceleration braking Reloading Available not available Reloading clock selection Reloading register 8 bits RLD CAP...

Page 360: ...ue Address Timer R mode register 1 TMRM1 R W Byte H 00 H D118 Timer R mode register 2 TMRM2 R W Byte H 00 H D119 Timer R control status register TMRCS R W Byte H 03 H D11F Timer R capture register 1 T...

Page 361: ...Not Clearing of TMRU 2 CLR2 This bit is used for selecting if the TMRU 2 counter reading is to be cleared or not as it is captured Bit 7 CLR2 Description 0 TMRU 2 counter reading is not to be cleared...

Page 362: ...the CFG Initial value 1 Reloading by underflowing of the TMRU 2 Bits 3 and 2 Selecting the Clock Source for the TMRU 2 PS21 and PS20 These bits work to select the inputting clock to the TMRU 2 Bit 3...

Page 363: ...LAT PS31 PS30 CP SLM CAPF SLW Bit Initial value R W The timer R mode register 2 TMRM2 is an 8 bit read write register which works to identify the operation mode and to control the slow tracking proce...

Page 364: ...ng the Clock Source for the TMRU 1 PS11 and PS10 These bits work to select the inputting clock to the TMRU 1 Bit 6 Bit 5 PS11 PS10 Description 0 Counting at the rising edge of the CFG Initial value 0...

Page 365: ...der the low power consumption mode Bit 1 CAPF Description 0 Clearing conditions Initial value When 0 is written after reading 1 1 Setting conditions At occurrences of the TMRU 2 capture signals while...

Page 366: ...pt when an interrupt cause being selected by the CP SLM bit of the TMRM2 has occurred such as occurrences of the TMRU 2 capture signals or when the slow tracking mono multi processing ends and the TMR...

Page 367: ...ccurrences of the TMRU 2 capture signals or ending of the slow tracking mono multi processing Bit 4 TMRI3 Description 0 Clearing conditions Initial value When 0 is written after reading 1 1 Setting co...

Page 368: ...ster 1 TMRCP1 works to store the capture data of the TMRU 1 During the course of the capturing operation the TMRU 1 counter readings are captured by the TMRCP1 at the CFG edge or the IRQ3 edge The cap...

Page 369: ...ention to the timing for reading out 2 When a shift to the low power consumption mode is made the counter reading becomes unstable After returning to the active mode always write H FF into the TMRL2 t...

Page 370: ...the TMRL2 is initialized to H FF 16 2 8 Timer R Load Register 3 TMRL3 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 W TMR37 W TMR36 W TMR35 W TMR34 W TMR33 W TMR32 W TMR31 W TMR30 Bit Initial value R W The timer R...

Page 371: ...MSTPCR are 8 bit read write twin registers which work to control the module stop mode When the MSTP11 bit is set to 1 the Timer R stops its operation at the ending point of the bus cycle to shift to t...

Page 372: ...Reload Timer When a value is written into to the reloading register the same value will be written into the counter simultaneously Also when the counter underflows the reloading register value will be...

Page 373: ...choose from among edges of the CFG edges of the IRQ3 or the underflow signals of the TMRU 3 It is possible to issue the TMRI3 interrupt request by the capture signal The capturing function stopping t...

Page 374: ...o identify the mode being searched For exemplary settings for the register see section 16 5 1 Mode Identification 16 3 5 Reeling Controls CFG counts can be captured by making 16 bit capturing operatio...

Page 375: ...tion has been finished when the CFG signal is not input even when the prescribed time has elapsed underflowing of down counting has occurred interrupt request will be issued because of the underflowin...

Page 376: ...tions Braking process Acceleration process Slow tracking delay C Rotary H AmpSW Accelerating the capstan motor Braking the drum motor Slow tracking moto multi Braking the capstan motor Servo Hi Z Lege...

Page 377: ...gister 1 TMRM1 to 0 c Interrupts being caused by the capture signals of the TMRU 3 and by ending the slow tracking mono multi process TMRI3 Since these two interrupt causes are constituting the OR it...

Page 378: ...settings 1 Setting the timer R mode register 1 TMRM1 CLR2 bit Bit 7 1 Works to clear after making the TMRU 2 capture RLD bit Bit 5 0 Sets the TMRU 3 without reloading function PS21 and PS20 Bits 3 an...

Page 379: ...dge of the IRQ3 signal is to be used as the capture signal for the TMRU 1 and TMRU 2 PS11 and PS10 Bits 6 and 5 0 and 0 The rising edge of the CFG signal is to be used as the clock source for the TMRU...

Page 380: ...ng mono multi function Exemplary settings for the acceleration process 1 Setting the timer R mode register 1 TMRM1 AC BR bit Bit 6 1 Acceleration process RLD bit Bit 5 1 The TMRU 2 is to be used as th...

Page 381: ...2 Set the count reading for the duration until the braking process finishes When the count is n the set value should be n 1 Regarding the duration until the braking process finishes see figure 16 2 Ex...

Page 382: ...r your selection You can select from among three different types of internal clocks 4 16 and 64 and the DVCFG Two independent output comparing functions Capable of outputting two different types of in...

Page 383: ...W FTIB VD FTIC DVCTL FTID NHSW DVCFG 4 16 64 TCSRX FRC OCRA OCRB TCRX TOCR ICRA ICRB ICRC ICRD Timer interrupt enabling register Timer control status register X Free running counter Output comparing r...

Page 384: ...ut Output pin for the output comparing A Output comparing B output pin FTOB Output Output pin for the output comparing B Input capture A input pin FTIA Input Input pin for the input capture A Input ca...

Page 385: ...aring register BL OCRBL R W H FF H D105 2 Timer control register X TCRX R W H 00 H D106 Timer output comparing control register TOCR R W H 00 H D107 Input capture register AH ICRAH R H 00 H D108 Input...

Page 386: ...inputting internal clock external clock The inputting clock is to be selected from the CKS1 and CKS0 of the TCRX By the setting of the CCLRA bit of the TCSRX the FRC can be cleared by comparing match...

Page 387: ...and when the value of these two match the OCFA and OCRB of the TCSRX will be set to 1 At this time if the OCIAE and OCIB of the TIER are being set to 1 an interrupt request will be issued to the CPU...

Page 388: ...e if the IDIAE through IDIDE of the TCRX are all being set to 1 due interrupt request will be issued to the CPU The edge of the input signal can be selected by setting the IEDGA through IEDGD of the T...

Page 389: ...Captures at both rising and falling edges of the input capture input A 1 1 Captures at the rising edge of the input capture input A Reading can be made from the ICR through the CPU at 8 bit or 16 bit...

Page 390: ...FA when the ICFA of the TCSRX is being set to 1 Bit 7 ICIAE Description 0 Prohibits interrupt requests ICIA by the ICFA Initial value 1 Permits interrupt requests ICIA by the ICFA Bit 6 Enabling the I...

Page 391: ...escription 0 Prohibits interrupt requests OCIA by the OCFA Initial value 1 Permits interrupt requests OCIA by the OCFA Bit 2 Enabling the Output Comparing Interrupt B OCIBE This bit works to permit pr...

Page 392: ...Input Capture A Signals ICSA This bit works to select the input capture A signals Bit 0 ICSA Description 0 Selects the FTIA pin for inputting of the input capture A signals Initial value 1 Selects th...

Page 393: ...d depending on the pin status or on the type of the detecting edge To avoid such error clear the interrupt requesting flag once immediately after shifting to the active mode from the low power consump...

Page 394: ...f ICFB 1 1 Setting conditions When the value of the FRC has been transferred to the ICRB by the input capture signals Bit 5 Input Capture Flag C ICFC This is a status flag indicating the fact that the...

Page 395: ...s not possible to make this setting using a software Bit 4 ICFD Description 0 Clearing conditions Initial value When 0 is written into the ICFD after reading the ICFD under the setting of ICFD 1 1 Set...

Page 396: ...OVF This is a status flag indicating the fact that the FRC overflowed H FFFF H 0000 This flag should be cleared by use of the software Such setting should only be made by use of the hardware It is not...

Page 397: ...on 0 Captures the falling edge of the input capture signal A Initial value 1 Captures the rising edge of the input capture signal A Bit 6 Input Capture Signal Edge Selection B IEDGB This bit works to...

Page 398: ...g the ICRC as the buffer register for the ICRA Bit 2 Buffer Enabling B BUFEB This bit works to select if or not to use the ICRD as the buffer register for the ICRB Bit 2 BUFEB Description 0 Using the...

Page 399: ...e mode Bit 7 Selecting the Input Capture B Signals ICSB This bit works to select the input capture B signals Bit 7 ICSB Description 0 Selects the FTIB pin for inputting of the input capture B signals...

Page 400: ...rol the output comparing A signals Bit 3 OEA Description 0 Prohibits the output comparing A signal outputs Initial value 1 Permits the output comparing A signal outputs Bit 2 Enabling the Output B OEB...

Page 401: ...t 0 Output Level B OLVLB This bit works to select the output level to output through the FTOB pin by use of the comparing match B matching signal between the FRC and OCRB Bit 0 OLVLB Description 0 Low...

Page 402: ...consists of twin 8 bit read write registers and it works to control the module stop mode When the MSTP10 bit is set to 1 the Timer X1 stops its operation at the ending point of the bus cycle to shift...

Page 403: ...0000 to start counting up The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX The inputs are transfe...

Page 404: ...64 generated by dividing the system clock can be selected Figure 17 3 shows the timing chart at this time FRC Internal clock FRC input clock N N 1 N 1 Figure 17 3 Count Timing in Case of Internal Clo...

Page 405: ...paring signal outputting A FRC OLVLA FTOA Output comparing signal outputting A pin N N Clearing 1 N N N 1 N 1 Comparing match signal OCRA Note 1 Execution of the command is to be designated by the sof...

Page 406: ...7 Input Capture Signal Inputting Timing under normal state 2 Input Capture Signal Inputting Timing when Making Buffer Operation Buffer operation can be made using the ICRA or ICRD as the buffer of th...

Page 407: ...ted with the input capture signals C and if the ICIEC bit is duly set an interrupt request will be issued However in this case the FRC value will not be transferred to the ICRC 17 3 6 Input Capture Fl...

Page 408: ...tching count reading After the values of the OCRA OCRB and FRC match up until the count up clock signal is generated the comparing match signal will not be issued Figure 17 10 shows the OCFA and OCFB...

Page 409: ...le stop FRC Reset Functions Functions Reset Reset Reset Reset Reset OCRA OCRB Reset Functions Functions Reset Reset Reset Reset Reset ICRA to ICRD Reset Functions Functions Reset Reset Reset Reset Res...

Page 410: ...of respective interrupt enabling bits of the TIER Also independent vector addresses are being allocated to respective interrupt causes Table 17 5 Interrupt Causes of the Timer X1 Abbreviations of the...

Page 411: ...ase difference of the pulses of the 50 duty For this setting follow the procedures listed below 1 set the CCLRA bit of the TCSRX to 1 2 Each time a comparing match occurs the OLVIA bit and the OLVLB b...

Page 412: ...ith the FRC When a counter clearing signal is issued under the T2 state where the FRC is under the writing cycle writing into the FRC will not be effected and the priority will be given to clearing of...

Page 413: ...C is under the writing cycle the counting up will not be effected and the priority will be given to count writing Figure 17 14 shows the timing chart in this case Address FRC address Internal writing...

Page 414: ...writing cycle the priority will be given to writing of the OCR and the comparing match signal will be prohibited Figure 17 15 shows the timing chart in this case Address OCR address Internal writing s...

Page 415: ...em clock For this reason like Item No 3 of table 17 6 count clock signals are issued deeming the timing before the changeover as the falling edge to have the FRC to count up Also when changing over be...

Page 416: ...Clock after the changeover Count clock FRC Re writing of the CKS1 and CKS0 N N 1 N 2 4 High High level changeover Clock before the changeover Clock after the changeover Count clock FRC Re writing of t...

Page 417: ...Rev 2 0 11 00 page 390 of 1037...

Page 418: ...t signal When this watchdog function is not needed the WDT can be used as an interval timer In interval timer mode an interval timer interrupt is generated each time the counter overflows 18 1 1 Featu...

Page 419: ...ternal reset signal WTCNT WTCSR 2 64 128 512 2048 8192 32768 131072 Clock Clock select Internal clock source Bus interface Module bus WTCSR WTCNT Note The internal reset signal can be generated by mea...

Page 420: ...DT Registers Address 1 Name Abbrev R W Initial Value Write 2 Read Watchdog timer control status register WTCSR R W 3 H 00 H FFBC H FFBC Watchdog timer counter WTCNT R W H 00 H FFBC H FFBD System contr...

Page 421: ...when the TME bit is cleared to 0 Note WTCNT is write protected by a password to prevent accidental overwriting For details see section 18 2 4 Notes on Register Access 18 2 2 Watchdog Timer Control St...

Page 422: ...WDT is used as a watchdog timer or interval timer If used as an interval timer the WDT generates an interval timer interrupt request WOVI when TCNT overflows If used as a watchdog timer the WDT gener...

Page 423: ...its 2 to 0 Clock Select 2 to 0 CKS2 to CKS0 These bits select an internal clock source obtained by dividing the system clock for input to WTCNT WDT input clock selection Bit 2 Bit 1 Bit 0 Description...

Page 424: ...d by watchdog timer overflow 1 Reset is generated by external reset input Initial value 18 2 4 Notes on Register Access The watchdog timer s WTCNT and WTCSR registers differ from other registers in be...

Page 425: ...Address H FFBC H 5A Write data 15 8 7 0 0 H A5 Write data 15 8 7 0 0 Figure 18 2 Format of Data Written to WTCNT and WTCSR 2 Reading WTCNT and WTCSR These registers are read in the same way as other r...

Page 426: ...or The reset source can be identified from the value of the XRST bit in SYSCR If a reset caused by an input signal from the 5 6 pin and a reset caused by WDT overflow occur simultaneously the 5 6 pin...

Page 427: ...is generated each time WTCNT overflows provided that the WDT is operating as an interval timer as shown in figure 18 4 This function can be used to generate interrupt requests at regular intervals WT...

Page 428: ...ion At the same time an interval timer interrupt WOVI is requested This timing is shown in figure 18 5 If NMI request generation is selected in watchdog timer mode when WTCNT overflows the OVF bit in...

Page 429: ...cted in watchdog timer mode an overflow generates an NMI interrupt request 18 5 Usage Notes 18 5 1 Contention between Watchdog Timer Counter WTCNT Write and Increment If a timer counter clock pulse is...

Page 430: ...the watchdog timer by clearing the TME bit to 0 before changing the value of bits CKS2 to CKS0 18 5 3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdo...

Page 431: ...Rev 2 0 11 00 page 404 of 1037...

Page 432: ...6 state Duty control method 19 1 2 Block Diagram Figure 19 1 shows a block diagram of the 8 bit PWM 1 channel PWMn n 3 to 0 20 27 OVF Match signal Legend PWRn PW8CR 8 bit PWM data register n 8 bit PWM...

Page 433: ...e output 2 8 bit PWM square wave output pin 3 PWM3 Output 8 bit PWM square wave output 3 19 1 4 Register Configuration Table 19 2 shows the 8 bit PWM register configuration Table 19 2 8 Bit PWM Regist...

Page 434: ...itial value R W 4 PWR3 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 6 0 7 PW34 PW33 PW32 PW31 PW30 0 W PW37 W W W PW36 PW35 Bit Initial value R W 8 bit PWM data registers 0 1 2 and 3 PWR0 PWR1 PWR2 PWR3 control th...

Page 435: ...le writable register that controls PWM functions PW8CR is initialized to H 00 by a reset Bits 7 to 4 Reserved They are always read as 1 Writes are disabled Bits 3 to 0 Output Polarity Select PWC3 to P...

Page 436: ...3 Switching is specified for each bit The PMR3 is a 8 bit readable writable register and is initialized to H 00 by a reset For bits other than 5 to 2 see section 11 5 Port 3 Bits 5 to 2 P35 PWM3 to P...

Page 437: ...tial value R W The MSTPCR consists of two 8 bit readable writable registers that control module stop mode When MSTP4 bit is set to 1 the 8 bit PWM stops its operation upon completion of the bus cycle...

Page 438: ...tegration in a low pass filter Figure 19 2 shows the output waveform example of 8 bit PWM The pulse width Twidth can be obtained by the following expression Twidth 1 PWR setting value T width Pulse wi...

Page 439: ...Rev 2 0 11 00 page 412 of 1037...

Page 440: ...o on chip 12 bit PWM signal generators are provided to control motors These PWMs use the pulse pitch control method periodically overriding part of the output This reduces low frequency components in...

Page 441: ...egister Low frequency components are reduced because the two quantizing pulses have different frequencies The error data is represented by an unsigned 12 bit binary number Internal data bus Legend CAP...

Page 442: ...M Output 12 bit PWM square wave output 20 1 4 Register Configuration Table 20 2 shows the 12 bit PWM register configuration Table 20 2 12 Bit PWM Registers Name Abbrev R W Size Initial Value Address C...

Page 443: ...ster for the drum motor Both are 8 bit writable registers CPWCR and DPWCR are initialized to H 42 by a reset or in sleep mode standby mode watch mode subactive mode subsleep mode or module stop mode o...

Page 444: ...utput 1 1 High impedance 0 Modulation signal output Note Don t care Bit 3 Output Data Select SF DF Selects whether the data to be converted to PWM output is taken from the data register or from the di...

Page 445: ...to 0 Carrier Frequency Select CK2 to CK0 Selects the carrier frequency of the PWM modulated signal Do not set them to 111 Bit 2 Bit 1 Bit 0 CK2 CK1 CK0 Description 0 2 0 1 4 0 8 Initial value 0 1 1 1...

Page 446: ...bit PWM data registers CPWDR and DPWDR are 12 bit readable writable registers in which the data to be converted to PWM output is written The data in these registers is converted to PWM output only wh...

Page 447: ...ers that control module stop mode When the MSTP1 bit is set to 1 the 12 bit PWM and Servo circuit stops their operation upon completion of the bus cycle and transits to the module stop mode For detail...

Page 448: ...on the size of the error When the motor is running ahead of the correct speed or phase it is corrected by periodically holding part of the PWM signal high The part held high depends on the size of the...

Page 449: ...esponds to Pwr1 1 Corresponds to Pwr0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Pwr3 2 1 0 L 2 3 4 5 6 7 8 9 10...

Page 450: ...can be used for V synthesizer etc 21 1 1 Features Features of the 14 bit PWM are given below Choice of two conversion periods A conversion period of 32768 with a minimum modulation width of 2 or a co...

Page 451: ...PWDRU PWM waveform generator PWM14 Figure 21 1 Block Diagram of 14 Bit PWM 21 1 3 Pin Configuration Table 21 1 shows the 14 bit PWM pin configuration Table 21 1 Pin Configuration Name Abbrev I O Func...

Page 452: ...14 bit PWM register configuration Table 21 2 14 Bit PWM Registers Name Abbrev R W Size Initial Value Address PWM control register PWCR R W Byte H FE H D122 PWM data register U PWDRU W Byte H 00 H D12...

Page 453: ...functions PWCR is initialized to H FE by a reset Bits 7 to 1 Reserved They are always read as 1 Writes are disabled Bit 0 Clock Select PWCR0 Selects the clock supplied to the 14 bit PWM Bit 0 PWCR0 De...

Page 454: ...r 6 bits assigned to PWDRU and the lower 8 bits to PWDRL The value written in PWDRU and PWDRL gives the total high level width of one PWM waveform cycle Both PWDRU and PWDRL are accessible by byte acc...

Page 455: ...dule stop control register MSTPCR consists of two 8 bit readable writable registers that control the module stop mode functions When the MSTP5 bit is set to 1 the 14 bit PWM operation stops at the end...

Page 456: ...in the PWM waveform generator and the PWM waveform generation data is updated in synchronization with internal signals One conversion period consists of 64 pulses as shown in figure 21 2 The total hig...

Page 457: ...Rev 2 0 11 00 page 430 of 1037...

Page 458: ...nput clocks Stable oscillation wait time count During the return from the low power consumption mode excluding the sleep mode the FRC counts the stable oscillation wait time 8 bit PWM The lower 8 bits...

Page 459: ...ternal data bus MSB LSB w 4 w 8 w 16 w 32 32 16 8 4 Interrupt request 5 bit counter IC pin Stable oscillation wait time count output 212 215 28 217 27 28 TMOW pin MSB LSB 8 bits 6 bits 8 bits PWM2 PWM...

Page 460: ...input pin Frequency division clock output TMOW Output Prescalar unit frequency division clock output pin 22 1 4 Register Configuration Table 22 2 shows the register configuration of the prescalar unit...

Page 461: ...scalar Unit Control Status Register PCSR 0 0 1 0 R W 2 0 R W 3 1 4 0 R W 5 0 6 0 7 R W R W ICEG R W ICIE 0 R W ICIF NCon off DCS2 DCS1 DCS0 Note Only 0 can be written to clear the flag Bit Initial val...

Page 462: ...ge Select ICEG ICEG selects the input edge sense of the pin Bit 5 ICEG Description 0 Detects the falling edge of the pin input Initial value 1 Detects the rising edge of the pin input Bit 4 Noise Canc...

Page 463: ...to DCS0 select eight types of frequency division clocks that are output from the TMOW pin Bit 2 Bit 1 Bit 0 DCS2 DCS1 DCS0 Description 0 Outputs PSS 32 Initial value 0 1 Outputs PSS 16 0 Outputs PSS 8...

Page 464: ...Initial value 1 The P17 TMOW pin functions as a TMOW pin for division clock output Bit 6 P16 Pin Switching PMR16 PMR16 sets whether the P16 pin is used as a P16 I O pin or an pin for the input captur...

Page 465: ...mented by one clock The PSS output is shared by the timer and serial communication interface SCI and the frequency division ratio can independently be set by each built in peripheral function When res...

Page 466: ...TMA2 bits of the timer mode register A TMA to 11 Note When the timer A is in module stop mode the operation is stopped Figure 22 2 shows the supply of the clocks to the peripheral function by the PSS...

Page 467: ...se Cancel Circuit An interrupt request is generated due to the input capture using the pin Note Rewriting the ICEG bit NCon off bit or PMR16 bit is incorrectly recognized as edge detection according t...

Page 468: ...ronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication function is provided that enab...

Page 469: ...transmitter and the receiver enabling continuous transmission and continuous reception of serial data 3 Built in baud rate generator allows any bit rate to be selected 4 Choice of serial clock source...

Page 470: ...gister Receive data register1 Transmit shift register Transmit data register1 Serial mode register1 Serial control register1 Serial status register1 Serial interface mode register1 Bit rate register1...

Page 471: ...us mode or synchronous mode the data format and the bit rate and to control the transmitter receiver Table 23 2 SCI Registers Channel Name Abbrev R W Initial Value Address 1 Serial mode register 1 SMR...

Page 472: ...2 Receive Data Register RDR1 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 0 R 2 0 R 1 0 R Bit Initial value R W RDR1 is a register that stores received serial data When the SCI1 has received one byte of serial da...

Page 473: ...in SSR1 is set to 1 TSR cannot be directly read or written to by the CPU 23 2 4 Transmit Data Register TDR1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W TDR1...

Page 474: ...mode watch mode subactive mode subsleep mode and module stop mode Bit 7 Communication Mode C Selects asynchronous mode or clock synchronous mode as the SCI1 operating mode Bit 7 C Description 0 Asynch...

Page 475: ...and checking The O bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking in asynchronous mode The O bit setting is invalid in synchronous mode when parity bi...

Page 476: ...of a transmit character before it is sent In reception only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit if it is 0 it is tr...

Page 477: ...that performs enabling or disabling of SCI1 transfer operations serial clock output in asynchronous mode and interrupt requests and selection of the serial clock source SCR1 can be read or written to...

Page 478: ...start of serial transmission by the SCI1 Bit 5 TE Description 0 Transmission disabled 1 Initial value 1 Transmission enabled 2 Notes 1 The TDRE flag in SSR1 is fixed at 1 2 In this state serial transm...

Page 479: ...interrupts when the TIE and RIE bits in SCR1 are set to 1 and FER and ORER flag setting is enabled Bit 2 Transmit End Interrupt Enable TEIE Enables or disables transmit end interrupt TEI request gener...

Page 480: ...al clock input Notes 1 Initial value 2 Outputs a clock of the same frequency as the bit rate 3 Inputs a clock with a frequency 16 times the bit rate 23 2 7 Serial Status Register SSR1 7 TDRE 1 R W 6 R...

Page 481: ...1 Bit 6 Receive Data Register Full RDRF Indicates that the received data is stored in RDR1 Bit 6 RDRF Description 0 Clearing conditions Initial value When 0 is written in RDRF after reading RDRF 1 1 S...

Page 482: ...nsmission cannot be continued either Bit 4 Framing Error FER Indicates that a framing error occurred during reception in asynchronous mode causing abnormal termination Bit 4 FER Description 0 Clearing...

Page 483: ...en the RE bit in SCR1 is cleared to 0 2 If a parity error occurs the receive data is transferred to RDR1 but the RDRF flag is not set Also subsequent serial reception cannot be continued while the PER...

Page 484: ...t to be added to the transmit data The MPBT bit setting is invalid when a multiprocessor format is not used when not transmitting and in synchronous mode Bit 0 MPBT Description 0 Data with a 0 multipr...

Page 485: ...0 13 2 48 0 15 0 00 0 19 2 34 9600 0 6 2 48 0 7 0 00 0 9 2 34 19200 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 0 2 0 00 38400 0 1 0 00 Operating Frequency MHz 3 6864 4 4 9152 5 Bit Rate bits s n N Error n N E...

Page 486: ...79 0 00 0 95 0 00 0 103 0 16 4800 0 38 0 16 0 39 0 00 0 47 0 00 0 51 0 16 9600 0 19 2 34 0 19 0 00 0 23 0 00 0 25 0 16 19200 0 9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 7 0 00 384...

Page 487: ...249 2 124 2 5 k 0 199 1 99 1 199 1 249 5 k 0 99 0 199 1 99 1 124 10 k 0 49 0 99 0 199 0 249 25 k 0 19 0 39 0 79 0 99 50 k 0 9 0 19 0 39 0 49 100 k 0 4 0 9 0 19 0 24 250 k 0 1 0 3 0 7 0 9 500 k 0 0 0 1...

Page 488: ...g frequency MHz n Baud rate generator input clock n 0 to 3 See the table below for the relation between n and the clock SMR1 Setting n Clock CKS1 CKS0 0 0 0 1 4 0 1 2 16 1 0 3 64 1 1 The bit rate erro...

Page 489: ...quency Asynchronous Mode MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 19...

Page 490: ...0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 5 1 2500 78125 6 1 5000 83750 6 144 1 5360 96000 7 3728 1 8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 Table 23...

Page 491: ...serial parallel conversion format Bit 3 SDIR Description 0 TDR1 contents are transmitted LSB first Initial value Receive data is stored in RDR1 LSB first 1 TDR1 contents are transmitted MSB first Rec...

Page 492: ...W 0 1 R W MSTPCRH MSTPCRL MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Bit Initial value R W MSTPCR comprising two 8 bit readable writable regi...

Page 493: ...ters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI1 clock source When inter...

Page 494: ...0 1 8 bit data 2 bits 0 1 bit 0 1 1 1 Asynchro nous mode multi processor format 7 bit data Yes 2 bits 1 Clock synchronous mode 8 bit data No No Table 23 9 SMR1 and SCR1 Settings and SCI1 Clock Source...

Page 495: ...ission line is usually held in the mark state high level The SCI1 monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication On...

Page 496: ...OP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOPSTOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP S...

Page 497: ...able 23 9 When an external clock is input at the SCK1 pin the clock frequency should be 16 times the bit rate used When the SCI1 is operated on an internal clock the clock can be output from the SCK1...

Page 498: ...ows a sample SCI1 initialization flowchart Wait Initialization completed Start initialization Set data transfer format in SMR1 and SCMR1 1 Set CKE1 and CKE0 bits in SCR1 TE RE bits 0 No Yes Set value...

Page 499: ...SCI1 initialization The SO1 pin is automatically designated as the transmit data output pin SCI1 status check and transmit data write Read SSR1 and check that the TDRE flag is set to 1 then write tran...

Page 500: ...n or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s One or two 1 bits stop bits are output e...

Page 501: ...a Parity bit Stop bit TXI interrupt request generated Data written to TDR1 and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated Idle state mark state TXI interr...

Page 502: ...or occurs read the ORER PER and FER flags in SSR1 to identify the error After performing the appropriate error handling ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be...

Page 503: ...ling Parity error handling Yes No Clear ORER PER and FER flags in SSR1 to 0 No Yes No Yes Framing error handling No Yes Overrun error handling ORER 1 FER 1 Break PER 1 Clear RE bit in SCR1 to 0 Figure...

Page 504: ...ata is stored in RDR1 If a receive error is detected in the error check the operation is as shown in table 23 11 Note Subsequent receive operations cannot be performed when a receive error has occurre...

Page 505: ...out each receiving station is addressed by a unique ID code The serial communication cycle consists of two component cycles an ID transmission cycle which specifies the receiving station and a data tr...

Page 506: ...ommunication line Serial data ID transmission cycle receiving station specification Data transmission cycle data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Mult...

Page 507: ...atus check and transmit data write Read SSR1 and check that the TDRE flag is set to 1 then write transmit data to TDR1 Set the MPBT bit in SSR1 to 0 or 1 Finally clear the TDRE flag to 0 Serial transm...

Page 508: ...ta 8 bit or 7 bit data is output in LSB first order c Multiprocessor bit One multiprocessor bit MPBT value is output d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output contin...

Page 509: ...andling routine TEI interrupt request generated Idle state mark state TXI interrupt request generated Start bit Multi processor bit Stop bit Start bit Stop bit 1 Multi processor bit Figure 23 11 Examp...

Page 510: ...and check that the RDRF flag is set to 1 then read the receive data in RDR1 and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF f...

Page 511: ...ER flags in SSR1 to 0 No Yes No Yes Framing error handling Overrun error handling ORER 1 FER 1 Break Clear RE bit in SCR1 to 0 5 Figure 23 12 Sample Multiprocessor Serial Reception Flowchart 2 Figure...

Page 512: ...its state ID1 a Data does not match station s ID MPIE RDR1 value 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1 1 Data ID2 Start bit MPB Stop bit Start bit Data Data 2 MPB Stop bit RXI interrupt request multi proces...

Page 513: ...4 Data Format in Clock Synchronous Communication In clock synchronous serial communication data on the transmission line is output from one falling edge of the serial clock to the next Data is guarant...

Page 514: ...bit to 0 does not change the settings of the RDRF PER FER and ORER flags or the contents of RDR1 Figure 23 15 shows a sample SCI1 initialization flowchart Wait Transfer start Start initialization Set...

Page 515: ...SSR1 3 Clear TE bit in SCR1 to 0 TDRE 1 All data transmitted TEND 1 SCI1 initialization The SO1 pin is automatically designated as the transmit data output pin SCI1 status check and transmit data writ...

Page 516: ...3 The SCI1 checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from TDR1 to TSR and serial transmission of the next frame is started If th...

Page 517: ...tion The following procedure should be used for serial data reception When changing the operating mode from asynchronous to synchronous be sure to check that the ORER PER and FER flags are all cleared...

Page 518: ...IF a receive error occurs read the ORER flag in SSR1 and after performing the appropriate error handling clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 SCI1 status ch...

Page 519: ...1 is set to 1 when the RDRF flag changes to 1 a receive data full interrupt RXI request is generated Also if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1 a receive error interrupt E...

Page 520: ...to TDR1 and clear the TDRE flag to 0 Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt Receive error handling If a receive error occurs read the ORER flag in SSR1 and...

Page 521: ...erated When the RDRF flag in SSR1 is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR1 is set to 1 an ERI interrupt request is generated Table 23 13 SCI1 Interrupt S...

Page 522: ...sferred from RSR to RDR1 and the receive data is lost Table 23 14 State of SSR1 Status Flags and Transfer of Receive Data SSR1 Status Flags RDRF ORER FER PER Receive Data Transfer RSR RDR1 Receive Err...

Page 523: ...when a receive error flag ORER PER or FER is set to 1 even if the TDRE flag is cleared to 0 Be sure to clear the receive error flags to 0 before starting transmission Note also that receive error flag...

Page 524: ...tio of bit rate to clock N 16 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F 0 and D 0 5 in equation 1 a receive margin of 46 875 is giv...

Page 525: ...Rev 2 0 11 00 page 498 of 1037...

Page 526: ...sfer can be automatically carried out Choice of 7 internal clocks 256 64 32 16 8 4 and 2 and an external clock as serial clock source Interrupt occurs when transmission has been completed or an error...

Page 527: ...strobe signal output pin SCR2 SCSR2 Serial control register 2 Serial control status register CS SO2 SCI2 chip select signal input pin SCI2 transmit data output pin SI2 SCI2 receive data input pin Int...

Page 528: ...utput SCI2 strobe signal output pin SCI2 Chip select 6 Input SCI2 chip select signal input pin 24 1 4 Register Configuration Table 24 2 shows register configuration of the SCI2 Table 24 2 Register Con...

Page 529: ...STAR are reserved writes are disabled When each bit is read 1 is read at all times The STAR is initialized to H E0 by a reset 24 2 2 Ending Address Register EDAR 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 5 6 1...

Page 530: ...rupt Enable TEIE Enables or disables the occurrence of transmit end interrupt when data transfer has been completed and TEI of the SCR2 has been set to 1 Bit 7 TEIE Description 0 Transmit end interrup...

Page 531: ...k Select 2 to 0 CKS2 to CKS0 Selects transfer clock Bit 2 Bit 1 Bit 0 Transfer clock cycle CKS2 CKS1 CKS0 SCK2 pin Clock source Prescaler division ratio 10 MHz 5 MHz 0 0 0 256 Initial value 25 6 s 51...

Page 532: ...retains the value of final bit of transfer data but the output level of the SO2 pin can be changed by operating this bit before or after transmission However setting of the SOL bit becomes invalid whe...

Page 533: ...rial data buffer 32 bytes has been executed during transmission and in the 6 input standby mode The instruction at that time is ignored and this bit is set to 1 Bit 2 WT Description 0 Clearing conditi...

Page 534: ...itial value 0 Write Transfer operation discontinues and the SCI2 is initialized Read During transfer operation or in 6 input standby mode 1 Write Transfer operation starts 24 2 5 Module Stop Control R...

Page 535: ...start of transfer and its forced cutoff can be controlled by 6 input Forced cutoff can be detected by the abort flag 24 3 1 Clock Selection of a transfer clock can be made from seven internal clocks...

Page 536: ...9 of 1037 SO2 SI2 SCK2 Start of transfer Bit 0 End of transfer CS STRB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 24 2 Transfer Format Transfer Da...

Page 537: ...7 SO2 SI2 SCK2 Start of transfer 8 24 and 56 clocks Bit 0 End of transfer CS STRB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 24 3 Transfer Format...

Page 538: ...utput on PMR2 Transfer clock and transfer data intervals can be set on SCR2 3 The starting and ending addresses in the transfer data area are set on STAR and EDAR If the value of the ending address is...

Page 539: ...ed synchronous clock is not output until the next STF is set During that time the SO2 pin continues to output the value of final bit of the immediately preceding data When an external clock is selecte...

Page 540: ...ting reception When reception has been completed synchronous clock is not output until the next STF is set When an external clock is selected data is received synchronized with the clock input from th...

Page 541: ...smission has been completed synchronous clock is not output until the next STF is set During that time the SO2 pin continues to output the value of final bit of the preceding data When an external clo...

Page 542: ...enable disable by setting TEIE of SCR2 While PMR30 of PMR3 is set to 1 transfer is cut off when the 6 pin enters a high level during data transfer and ABT of SCSR2 is set to 1 and then transfer cutoff...

Page 543: ...Rev 2 0 11 00 page 516 of 1037...

Page 544: ...election of acknowledge output levels when receiving I2 C bus format Automatic loading of acknowledge bit when transmitting I2 C bus format Wait function in master mode I2 C bus format A wait can be i...

Page 545: ...on the power Vcc voltage of this LSI SCL PS Noise canceller Bus state decision circuit Output data control circuit ICCR Clock control ICMR ICSR ICDRS Address comparator Arbitration decision circuit SA...

Page 546: ...out Slave 2 SDA VCC Figure 25 2 I 2 C Bus Interface Connections Example This Chip as Master 25 1 3 Pin Configuration Table 25 1 summarizes the input output pins used by the I 2 C bus interface Table 2...

Page 547: ...15E 2 I 2 C bus mode register ICMR R W H 00 H D15F 2 Slave address register SAR R W H 00 H D15F 2 Second slave address register SARX R W H 01 H D15E 2 Serial timer control register STCR R W H 00 H FFE...

Page 548: ...value R W ICDRR 7 ICDRR7 R 6 ICDRR6 R 5 ICDRR5 R 4 ICDRR4 R 3 ICDRR3 R 0 ICDRR0 R 2 ICDRR2 R 1 ICDRR1 R Bit Initial value R W ICDRS 7 ICDRS7 6 ICDRS6 5 ICDRS5 4 ICDRS4 3 ICDRS3 0 ICDRS0 2 ICDRS2 1 ICD...

Page 549: ...ers among the three registers are performed automatically in coordination with changes in the bus state and affect the status of internal flags such as TDRE and RDRF After transmission reception of on...

Page 550: ...detected in the bus line state after a stop condition is issued with the I 2 C bus format or serial format selected 3 When a stop condition is detected with the I 2 C bus format selected 4 In receive...

Page 551: ...de and the addressing format is selected if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition the chip operates as the slave device specified by the ma...

Page 552: ...r master mode only The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode SAR Bit 0 SARX Bit 0 FS FSX Operating Mode 0 I 2 C bus format SAR and SARX slave ad...

Page 553: ...ice SARX is assigned to the same address as ICDR and can be written and read only when the ICE bit is cleared to 0 in ICCR SARX is initialized to H 01 by a reset and in hardware standby mode Bits 7 to...

Page 554: ...and read only when the ICE bit is set to 1 in ICCR ICMR is initialized to H 00 by a reset Bit 7 MSB First LSB First Select MLS Selects whether data is transferred MSB first or LSB first If the number...

Page 555: ...h SCL at the low level When the IRIC flag is cleared to 0 in ICCR the wait ends and the acknowledge bit is transferred If WAIT is cleared to 0 data and acknowledge bits are transferred consecutively w...

Page 556: ...z 0 28 179 kHz 286 kHz 357 kHz 0 1 40 125 kHz 200 kHz 250 kHz 0 48 104 kHz 167 kHz 208 kHz 0 1 1 64 78 1 kHz 125 kHz 156 kHz 0 80 62 5 kHz 100 kHz 125 kHz 0 1 100 50 0 kHz 80 0 kHz 100 kHz 0 112 44 6...

Page 557: ...hould be made during an interval between transfer frames If bits BC2 to BC0 are set to a value other than 000 the setting should be made while the SCL line is low The bit counter is initialized to 000...

Page 558: ...is to be used When ICE is set to 1 port pins function as SCL and SDA input output pins and transfer operations are enabled When ICE is cleared to 0 the I 2 C bus interface module is disabled and the i...

Page 559: ...ter a start condition Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed and the changeover is made after completion of the...

Page 560: ...e ignored and continuous transfer is performed or transfer is to be aborted and error handling etc performed if the acknowledge bit is 1 When the ACKE bit is 0 the value of the received acknowledge bi...

Page 561: ...before writing 1 in BBSY and 0 in SCP Bit 2 BBSY Description 0 Bus is free Initial value Clearing condition When a stop condition is detected 1 Bus is busy Setting condition When a start condition is...

Page 562: ...knowledge bit when the ACKE bit is 1 when the ACKB bit is set to 1 I 2 C bus format slave mode 1 When the slave address SVA SVAX matches when the AAS and AASX flags are set to 1 and at the end of data...

Page 563: ...the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address SVA or general call address match in I 2 C bus format slave mode Even when the I...

Page 564: ...RX match 0 1 0 1 0 0 0 0 0 0 0 0 1 Slave mode transmit receive end except after SARX match 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 Slave mode transmit receive end after SARX match 0 1 0 0 1 0 1...

Page 565: ...tion and control ICSR is initialized to H 00 by a reset Bit 7 Error Stop Condition Detection Flag ESTP Indicates that a stop condition has been detected during frame transfer in I 2 C bus format slave...

Page 566: ...C bus format slave mode Bit 6 STOP Description 0 No normal stop condition Initial value Clearing condition 1 When 0 is written in STOP after reading STOP 1 2 When the IRIC flag is cleared to 0 1 In I...

Page 567: ...lag setting is performed when the TDRE or RDRF flag is set to 1 IRTR is cleared by reading IRTR after it has been set to 1 then writing 0 in IRTR IRTR is also cleared automatically when the IRIC flag...

Page 568: ...Lost AL This flag indicates that arbitration was lost in master mode The I 2 C bus interface monitors the bus When two or more master devices attempt to seize the bus at nearly the same time if the I...

Page 569: ...ve address or general call address recognized Setting condition When the slave address or general call address is detected in slave receive mode Bit 1 General Call Address Recognition Flag ADZ In I 2...

Page 570: ...output at acknowledge output timing Initial value Transmit mode Indicates that the receiving device has acknowledged the data signal is 0 1 Receive mode 1 is output at acknowledge output timing Transm...

Page 571: ...out making port settings or initializing registers For the detail refer to section 25 3 9 Initialization of Internal State The initialization is continuous and the I 2 C bus interface cannot operate w...

Page 572: ...eadable writable registers and is used to perform module stop mode control When the corresponding bit in MSTPCR is set to 1 operation of the corresponding I 2 C module is halted at the end of the bus...

Page 573: ...C bus timing The symbols used in figures 25 3 to 25 5 are explained in table 25 4 S A SLA 7 n R W DATA A 1 1 m 1 1 1 A A 1 P 1 Transfer bit count n 1 to 8 Transfer frame count m 1 or above S SLA 7 n1...

Page 574: ...e transmission procedure and operations synchronize with the ICDR writing are described below 1 Set bit ICE in ICCR to 1 Set bits MLS WAIT and CKS2 to CKS0 in ICMR and bit IICX in STCR according to th...

Page 575: ...Write the transmit data to ICDR As indicating the end of the transfer and so the IRIC flag is cleared to 0 After writing ICDR clear IRIC immediately not to execute other interrupt handling routine The...

Page 576: ...Geberation Slave address Data 1 9 ICDR write 9 IRIC clear 6 ICDR write 6 IRIC clear address R 7 5 Note Data write timing in ICDR ICDR Writing prohibited 4 Write BBSY 1 and SCP 0 start condition issuan...

Page 577: ...IRIC immediately not to execute other interrupt handling routine If one frame of data has been received before the IRIC clearing it can not be determine the end of reception 3 The IRIC flag is set to...

Page 578: ...WAIT 0 14 Clear the BBSY bit and SCP bit to 0 This changes SDA from low to high when SCL is high and generates the stop condition 9 A Bit7 Master receive mode Master transmit mode SCL master output S...

Page 579: ...7 IRIC clearance 9 IRIC Clearance 6 ICDR read Data 3 7 IRIC clearance Bit7 8 5 A Bit6 Bit5 Bit4 Bit7 Bit6 Bit3 Bit2 Bit1 Bit0 9 1 2 3 4 5 6 7 8 5 A 8 9 1 2 Data 3 Data 4 Data 3 Data 2 Data 1 These pr...

Page 580: ...ted as the master device If the 8th bit data R is 0 TRS bit in ICCR remains 0 and executes slave receive operation 4 At the ninth clock pulse of the receive frame the slave device drives SDA low to ac...

Page 581: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRIC ICDRS ICDRR RDRF SCL Master output Start condition issurance SCL Slave output Interrupt request generated Address R W Address R W 5 Read ICDR 5 Clear IRIC U...

Page 582: ...t 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 IRIC ICDRS ICDRR RDRF SCL Master output SCL Slave output Interrupt request generated Interrupt request generated Data 2 Data 2 Data 1 Data 1 5 Read ICDR 5 Clear...

Page 583: ...TDRE internal flag and the IRIC and IRTR flags are set to 1 again Clear IRIC to 0 then write the next data in ICDR The slave device outputs the written data serially in step with the clock output by t...

Page 584: ...Bit 0 IRIC ICDRS ICDRT TDRE SCL Master output Interrupt request generated Interrupt request generated Interrupt request generated Slave receive mode Slave transmit mode Data 1 Data 2 3 Clear IRIC 5 Cl...

Page 585: ...t different times depending on the WAIT bit in ICMR the FS bit in SAR and the FSX bit in SARX If the TDRE or RDRF internal flag is set to 1 SCL is automatically held low after one frame has been trans...

Page 586: ...te to ICDR transmit or read ICDR receive 1 A 8 1 9 8 Clear IRIC SCL SDA IRIC User processing Clear IRIC Write to ICDR transmit or read ICDR receive 1 8 7 1 8 7 a When WAIT 0 and FS 0 or FSX 0 I2 C bus...

Page 587: ...The SCL or SDA input signal is sampled on the system clock but is not passed forward to the next circuit unless the outputs of both latches agree If they do not agree the previous value is held SCL o...

Page 588: ...eceive mode Read IRIC in ICCR No IRIC 1 Clear IRIC in ICCR 1 Initialize 2 Test the status of the SCL and SDA lines 3 Select master transmit mode 4 Start condition issuance 5 Wait for a start condition...

Page 589: ...is a dummy read After reading ICDR please clear IRIC immediately 3 Wait for 1 byte to be received 8th clock falling edge 4 Clear IRIC to trigger the 9th clock to end the wait insertion 5 Wait for 1 b...

Page 590: ...and TRS 0 in ICCR IRIC 1 No Yes Read IRIC flag in ICCR Set ACKB 0 in ICSR IRIC 1 No Yes TRS 0 IRIC 1 No No Yes Yes Yes AAS 1 and ADZ 0 2 1 3 8 5 6 4 7 Slave transmit mode Last receive No No Yes Select...

Page 591: ...R Read IRIC flag in ICCR IRIC 1 Yes Yes No No 1 4 5 2 3 Slave transmit mode End of transmission ACKB 1 Clear IRIC in ICCR Set transmit data for the second and subsequent bytes Wait for 1 byte to be tr...

Page 592: ...nerated interrupt factors transferred to the interrupt controller 2 Precautions on Initialization Interrupt flags and interrupt factors are not cleared by this function Thus you need to clear them own...

Page 593: ...t initialization of internal state by setting IICRST bit or ICE bit 2 Execute the stop condition issue instruction setting BBSY 0 and SCP 0 to write and wait for a duration equivalent to 2 clocks of t...

Page 594: ...y the rise and fall times of signals affected by the bus load capacitance series resistance and parallel resistance Table 25 5 I 2 C Bus Timing SCL and SDA Output Item Symbol Output Timing Unit Notes...

Page 595: ...ns and 300 ns The I 2 C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc as shown in table 25 5 However because of the rise and fall times the I 2 C bus interface specifications...

Page 596: ...300 100 400 625 700 Normal mode 1000 250 1300 2200 2500 tSDASO slave 1tSCLL 3 12tcyc 2 tSr High speed mode 300 100 1400 1 500 1 200 1 Normal mode 0 0 600 375 300 tSDAHO 3tcyc High speed mode 0 0 Notes...

Page 597: ...received data after the stop condition issue instruction setting ICCR s BBSY 0 and SCP 0 to write has been executed but before the actual stop condition is generated clock may not be appropriately si...

Page 598: ...art condition issuance Other processing No 1 2 3 4 5 No No Yes Yes Yes Yes No 1 Wait for end of 1 byte transfer 2 Determine wheter SCL is low 3 Issue restart condition instruction for transmission 4 D...

Page 599: ...arge or if there is a slave device of the type that drives SCL low to effect a wait issue the stop condition instruction after reading SCL and determining it to be low as shown below As waveform rise...

Page 600: ...nverter that allows up to 12 analog input channels to be selected 26 1 1 Features A D converter features are listed below 10 bit resolution 12 input channels Sample and hold function Choice of softwar...

Page 601: ...HSW timing generator Internal data bus Legend ADR AHR Software trigger A D result register Hardware trigger A D result register ADTRG DFG ADTRG Hardware trigger A D external trigger input ADCR ADCSR...

Page 602: ...nnel 1 Analog input pin 2 AN2 Input Analog input channel 2 Analog input pin 3 AN3 Input Analog input channel 3 Analog input pin 4 AN4 Input Analog input channel 4 Analog input pin 5 AN5 Input Analog i...

Page 603: ...egister L ADRL R Byte H 00 H D131 Hardware trigger A D result register H AHRH R Byte H 00 H D132 Hardware trigger A D result register L AHRL R Byte H 00 H D133 A D control register ADCR R W Byte H 40...

Page 604: ...directly but the data in the lower bytes is transferred via a temporary register TEMP For details see section 26 3 Interface to Bus Master ADR is a 16 bit read only register which is initialized to H...

Page 605: ...upper bytes can always be read directly but the data in the lower bytes is transferred via a temporary register TEMP For details see section 26 3 Interface to Bus Master AHR is a 16 bit read only regi...

Page 606: ...e register that is initialized to H 40 by a reset and in module stop mode standby mode watch mode subactive mode and subsleep mode Bit 7 Clock Select CK Sets A D conversion speed Bit 7 CK Description...

Page 607: ...nstruction and executes interrupt exception handling after completing the instruction Figure 26 2 Internal Operation of A D Converter Bit 6 Reserved This bit cannot be modified and always reads 1 Writ...

Page 608: ...2 6 Port Mode Register 0 PMR0 Bit 3 Bit 2 Bit 1 Bit 0 SCH3 SCH2 SCH1 SCH0 Analog Input Channel 0 AN0 Initial value 0 1 AN1 0 AN2 0 1 1 AN3 0 AN4 0 1 AN5 0 AN6 0 1 1 1 AN7 0 AN8 0 1 AN9 0 ANA 0 1 1 AN...

Page 609: ...ggered A D result register ADR or hardware triggered A D result register AHR and the SST or HST bit is cleared to 0 If software triggering and hardware or external triggering are generated at the same...

Page 610: ...rted Bit 4 SST Description Read Indicates that software triggered A D conversion has ended or been stopped Initial value 0 Write Software triggered A D conversion is aborted Read Indicates that softwa...

Page 611: ...mpt to execute software triggered A D conversion while hardware or external triggered A D conversion was in progress Bit 1 Software Triggered Conversion Cancel Flag SCNL Indicates that software trigge...

Page 612: ...ersion is not in progress Bit 1 Bit 0 TRGS1 TRGS0 Description 0 Hardware or external triggered A D conversion is disabled Initial value 0 1 Hardware triggered ADTRG A D conversion is selected 0 Hardwa...

Page 613: ...MSTP3 R W 2 1 MSTP2 R W 1 1 MSTP1 R W 0 1 MSTP0 R W MSTPCRL Bit Initial value R W MSTPCR consists of 8 bit readable writable registers and performs module stop mode control When the MSTP2 bit in MSTP...

Page 614: ...e lower byte value is transferred to TEMP Next when the lower byte is read the TEMP contents are transferred to the CPU When reading ADR and AHR always read the upper byte before the lower byte It is...

Page 615: ...conversion end interrupt occurs If the conversion time or input channel selection in ADCR needs to be changed during A D conversion to avoid malfunctions first clear the SST bit to 0 to halt A D conv...

Page 616: ...n ADCR needs to be changed during A D conversion to avoid malfunctions first clear the HST flag to 0 to halt A D conversion If software writes 1 in the SST bit to start software triggered conversion w...

Page 617: ...1 The A D conversion end interrupt can be enabled or disabled by ADIE bit in ADCSR Figure 26 4 shows the block diagram of A D conversion end interrupt A D conversion end interrupt ADI To interrupt co...

Page 618: ...ess set appears during bus cycle 27 1 1 Features Address to trap can be set independently at three points 27 1 2 Block Diagram Figure 27 1 shows a block diagram of the address trap controller TRCR TAR...

Page 619: ...address register 2 TAR2 R W H F00000 H FFB6 to H FFB8 Note Lower 16 bits of the address 27 2 Register Descriptions 27 2 1 Address Trap Control Register ATCR 0 0 1 0 R W 2 0 R W 3 1 4 1 5 1 6 1 7 R W...

Page 620: ...bled 27 2 2 Trap Address Register 2 to 0 TAR2 to TAR0 0 0 1 0 R W 2 0 R W 3 4 5 6 7 R W A18 A17 A16 0 0 R W 0 R W R W A23 A22 A21 0 0 R W R W A20 A19 0 0 1 0 R W 2 0 R W 3 4 5 6 7 R W A10 A9 A8 0 0 R...

Page 621: ...internal address buses A23 to A1 match as a result of comparison an interruption occurs For the address to trap set to the address where the first byte of an instruction exists In the case of other ad...

Page 622: ...ruction prefetch 27 3 1 Basic Operations After terminating the execution of the instruction being executed in the second state from the trap address prefetch the address trap interrupt exception handl...

Page 623: ...on pre fetch Trap setting address The underlines address is the one to be actually stacked Figure 27 3 Basic Operations 2 3 Figure 27 4 shows the operation when the instruction immediately preceding t...

Page 624: ...the trap address is the next instruction to the Bcc instruction and the condition is satisfied by the Bcc instruction and then branched transition is made to the address trap interrupt after executin...

Page 625: ...d prefetching the next instruction The address to be stacked is 02A2 Address bus Interrupt request signal 029E 02A2 02A0 02A8 02A4 029E BEQ NEXT 8 02A0 NOP 02A2 NOP 02A4 NOP 02A6 NOP 02A8 CMP W R0 R1...

Page 626: ...nstruction is that of 1 state after executing two instructions The address to be stacked is 02C0 Address bus Interrupt request signal Start of exception handling 02B8 02C0 02BC 02BE 02C2 02BA 02B8 BEQ...

Page 627: ...is that of 1 state after executing two instructions The address to be stacked is 0262 Address bus Interrupt request signal Start of exception handling 025C 0262 0266 025E 0260 0264 025C BEQ NEXT 8 025...

Page 628: ...tching the instruction at the branch The address to be stacked is 02C2 Address bus Interrupt request signal BSR execution Stack saving 0294 SP 4 02C2 0296 SP 2 02C4 0294 BSR ER0 0296 NOP 0298 NOP 02C2...

Page 629: ...ap setting address The underlines address is the one to be actually stacked Figure 27 11 JSR Instruction Register indirect 2 JSR Instruction Memory indirect When the trap address is the next instructi...

Page 630: ...ch MOV instruc tion pre fetch Trap setting address The underlines address is the one to be actually stacked Figure 27 13 JMP Instruction Register Indirect 2 JMP Instruction Memory indirect When the tr...

Page 631: ...one to be actually stacked Figure 27 15 RTS Instruction 27 3 8 SLEEP Instruction 1 SLEEP Instruction 1 When the trap address is the SLEEP instruction and the instruction execution cycle immediately p...

Page 632: ...EEP mode NOP instruc tion pre fetch SLEEP instruc tion pre fetch NOP instruc tion pre fetch Trap setting address The underlines address is the one to be actually stacked Figure 27 17 SLEEP Instruction...

Page 633: ...pt following the CCR and PC at the address of 0266 stack saving and vector reading However if the address trap interrupt arises before starting execution of the NMI interrupt processing transition is...

Page 634: ...bus Interrupt request signal Address trap interrupt 0280 0282 0284 SP 2 SP 2 0280 NOP 0282 SLEEP 0284 NOP Trap setting address SLEEP execution NMI interruption Standby mode NOP instruc tion pre fetch...

Page 635: ...29A 029C 02A0 Address bus Interrupt request signal Data read Data read Start of ATC interrupt processing Set one of these to the trap address 2 029C NOP 0296 MOV B R2L Port 029A NOP 029E NOP 02A0 NOP...

Page 636: ...cessing The ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing The address to be stacked is 02E0 for the NMI and 340 for the ATC Whe...

Page 637: ...ss bus NMI interrupt request signal ATC interrupt request signal Start of ATC Interrupt processing 2 02DC 02E2 02E4 SP 4 SP 2 0340 Vector Vector Vector 02DE 02E0 0342 02E6 02E8 B A NMI interrupt proce...

Page 638: ...ng output 12 bit PWM Improved speed of carrier frequency Frequency division circuit With CFG mask no CFG for phase or CTL mask 1 Input and output circuits Sync detection circuit Noise count field disc...

Page 639: ...Rev 2 0 11 00 page 612 of 1037 28 1 2 Block Diagram Figure 28 1 shows a block diagram of the servo circuits...

Page 640: ...ty deter minator Assemble recording DVCFG DVCFG2 Gain up XE ON VD PR0 to 7 P60 to 67 Sync detector REC CTL generator VISS circuit Noise Det A D converter Timer X1 Timer L Timer R AN pins PWM X value a...

Page 641: ...ment by software DFG and DPG signals which are the signals to control the drum allow selection between separate or overlap input SV1 and SV2 pins allow to output to monitor the inside signals of the s...

Page 642: ...t Circuit The CFG input pin has built in an amplifier and a zero cross type comparator Figure 28 3 shows the input circuit of CFG CFGCOMP CFGCOMP P250 REF M250 S R F F O stp VREF VREF CFG BIAS CFG RES...

Page 643: ...ilt in an amplifier Figure 28 4 shows the input circuit of CTL CTLFB CTLSMT i CTLFB CTLREF CTLBias CTLGR0 CTLGR3 to 1 AMPSHORT REC CTL PB CTL Note Be sure to set a capacitor between CTLAmp o and CTLSM...

Page 644: ...signal input output CTL I O pin CTL I O CTL signal input output CTL Bias input pin CTLBias Input CTL primary amplifier bias supply CTL Amp O output pin CTLAMP O Output CTL amplifier output CTL SMT i...

Page 645: ...de Register SPMR 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 6 7 EXCTLON DPGSW COMP H Amp SW C Rot 0 R W CTLSTOP R W R W CFGCOMP 1 Bit Initial value R W A register to switch the servo port general purpose...

Page 646: ...pin Bit 4 EXCTLON Description 0 EXCTL PS4 pin functions as EXCTL input pin Initial value 1 EXCTL PS4 pin functions as PS4 I O Bit 3 DPG Pin Switching Bit DPGSW Selects the drum control system input s...

Page 647: ...Servo Control Register SPCR 0 0 1 0 W 2 0 W 3 0 4 0 W 5 6 7 SPCR4 SPCR3 SPCR2 SPCR1 SPCR0 W W 1 1 1 Bit Initial value R W Controls input and output of each pin PS4 to PS0 for each bit when the servo p...

Page 648: ...used as general purpose port If the port is accessed for read when SPCR is 1 output the SPDRn value is read directly Accordingly this register is not affected by the state of the pin If the port is ac...

Page 649: ...SVMCR4 SVMCR3 Description 0 Outputs REF30 signal to SV2 output pin Initial value 0 1 Outputs CAPREF30 signal to SV2 output pin 0 Outputs CREF signal to SV2 output pin 0 1 1 Outputs CTLMONI signal to...

Page 650: ...ead out It is initialized to H C0 by a reset or stand by Bit 7 to 6 Reserved Reserved bits writes are disabled If read was attempted an undetermined value is read out Bit 5 CTL Selection Bit CTLE Cont...

Page 651: ...B 0 39 0 dB 0 1 1 41 5 dB 0 44 0 dB 0 1 46 5 dB 0 49 0 dB 0 1 1 1 51 5 dB 0 54 0 dB 0 1 56 5 dB 0 59 0 dB 0 1 1 61 5 dB 0 64 0 dB 0 1 66 5 dB 0 69 0 dB 1 1 1 1 71 5 dB Note With a setting of 64 0 dB o...

Page 652: ...r was selected DPGSW 1 take care in the input levels of DFG and DPG Figure 28 5 shows DFG DPG input signals DPG DPG Schmitt level 3 45 3 55 VIL VIH DFG Schmitt level 1 85 1 95 VIL VIH DFG 1 DPG DFG se...

Page 653: ...an The CREF signal is used if the reference signal to control the phase of the capstan cannot be shared with the REF30 signal in REC mode Each signal generator consists of a 16 bit counter which has t...

Page 654: ...REF30P Video FF VD Match Mask Clear W R W W Internal bus R W Internal bus Toggle RCS REF30 counter register 16 bit OD EV VST FDS VEG Edge detec tion Edge detec tion VNA R W TBC CVS REX Reference perio...

Page 655: ...am of CREF Signal Generator 28 3 3 Register Configuration Table 28 4 shows the register configuration of the reference signal generators Table 28 4 Register Configuration Name Abbrev R W Size Initial...

Page 656: ...stop RFM is accessible by byte access only If accessed by a word its operation is not assured Bit 7 Clock Source Selection Bit RCS Selects the clock source supplied to the counter s fosc 2 Bit 7 RCS...

Page 657: ...Description 0 VD signals or free run Initial value 1 Sync with external signals Bit 3 DVCFG2 Sync Selection Bit CRD Selects whether the reset timing in the CREF signals generation is immediately afte...

Page 658: ...in FIX on in PB mode Bit 1 VST Description 0 Counter set off by Video FF signal Initial value 1 Counter set on by Video FF signal Bit 0 Video FF Edge Selection Bit VEG Selects the edge at which the R...

Page 659: ...eriod Care is required when VD is unstable such as when the field is weak Synchronization with VD cannot be acquired if a value less than 1 2 is set when in REC When data is written in RFD it is store...

Page 660: ...se bit 4 CR RF bit in the capstan phase error detection control register CPGCR to switch between REF30 and CREF for capstan phase control See section 28 9 Capstan Phase Error Detector 4 REF30 Counter...

Page 661: ...the reference signals are generated by VD or in free run in PB mode Bit 7 TBC Description 0 Reference signals are generated by VD This function is effective only in the H8S 2194C series 1 Reference si...

Page 662: ...n signal detected in the sync signal detection circuit Select which is used by setting bit 6 VNA or 5 CVS of RFM The phase of the toggle output of the REF30 signal is cleared to L level when the signa...

Page 663: ...28 8 28 9 28 10 28 11 and 28 12 show the timing of the generation of REF30 and REF30P signals Counter set Counter set Counter set Value set in reference period register 1 RFD Counter Value set in REF3...

Page 664: ...ister 1 RFD Selected VD OD EV 0 Counter mask clear signal mask Counter Value set in REF30 counter register RFC REF30 VD Toggle mask Field signal REF30P HSW Drum phase counter T About 75 Masking period...

Page 665: ...cted VD OD EV 0 Counter mask clear signal mask Counter Value set in REF30 counter register RFC REF30 VD Toggle mask Field signal REF30P HSW Drum phase counter Sampling T Sampling About 75 About 75 Abo...

Page 666: ...FD Selected VD OD EV 0 Counter mask clear signal mask Counter Value set in REF30 counter register RFC REF30 VD Toggle mask Field signal REF30P HSW Drum phase counter Sampling T Sampling About 75 About...

Page 667: ...aveform The counter of the CREF signal generator is initialized to H 0000 and the phase of the toggle is cleared to L level at the mode transition of PB ASM to REC The timing of clearing is selectable...

Page 668: ...Chart of the CREF Signal Generation Figures 28 13 28 14 and 28 15 show the generation of the CREF signal Cleared Cleared Cleared Value set in reference period register 2 CRF Counter Toggle signal CREF...

Page 669: ...42 of 1037 Cleared Cleared Cleared Value set in reference period register 2 CRF Counter Time period when CRF is set REC PB ASM Toggle signal REC PB CREF Figure 28 14 CREF Signal when PB is Switched to...

Page 670: ...of 1037 Cleared Cleared Cleared Value set in reference period register 2 CRF Counter Time period when CRF is set Toggle signal REC PB CREF DVCFG2 REC PB ASM Figure 28 15 CREF Signal when PB is Switche...

Page 671: ...ference period register 1 RFD Selected VD OD EV 0 When in the field discrimination mode Counter mask Clear signal mask Counter Value set in REF30 counter register RFC REF30 VD except in PB REC ASM PB...

Page 672: ...ounter mask Clear signal mask Counter Value set in REF30 counter register RFC REF30 VD except in PB REC ASM PB Toggle mask Field signal REC PB REF30P About 50 Cleared Cleared Cleared Cleared Masking p...

Page 673: ...Cleared Cleared Value set in reference period register 1 RFD FDS bit 1 Counter mask Clear signal mask Counter Value set in REF30 counter register RFC REF30 VD except in PB REC ASM PB Toggle mask REC...

Page 674: ...ask Clear signal mask Counter Value set in REF30 counter register RFC REF30 VD except in PB REC ASM PB Toggle mask REC PB REF30P Masking period Masking period 25 25 25 Figure 28 19 Generation of the R...

Page 675: ...1 RFD FDS bit 1 Counter mask Clear signal mask Counter Value set in REF30 counter register RFC REF30 VD except in PB REC ASM PB Toggle mask REC PB REF30P Masking period Masking period Max 25 Figure 28...

Page 676: ...1 RFD FDS bit 1 Counter mask Clear signal mask Counter Value set in REF30 counter register RFC REF30 VD except in PB REC ASM PB Toggle mask REC PB REF30P Masking period Masking period Max 25 Figure 28...

Page 677: ...g circuit compares the timing data in the most significant 16 bits of FIFO with the 16 bit timer and controls the output of pattern data set in the least significant 15 bits of FIFO The 16 bit timer i...

Page 678: ...SW loop stage number setting register Internal bus FGR20FF FRT CCLR Edge detector Control circuit FIFO 1 31 bits 10 stages 15 bits P77 to 70 PPG output FIFO timing pattern register 1 FIFO timing patte...

Page 679: ...FO status DFG count compare circuit 2 Detection of match between DFCR and DFG counters 16 bit timer counter 16 bit free run timer counter 31 bit x 20 stage FIFO First In First Out data buffer 31 bit F...

Page 680: ...Word Undetermined H FD06A DFG reference register 1 DFCRA W Byte Undetermined H FD06C DFG reference register 2 DFCRB W Byte Undetermined H FD06D FIFO timer capture register FTCTR R Word H 0000 H FD066...

Page 681: ...ern data and the output pattern data of FIFO1 are full If a write is attempted in this state the write operation becomes invalid an interrupt is generated the OVWA flag bit 2 is set to 1 and the write...

Page 682: ...FIFO1 Overwrite Flag OVWA If a write is attempted when the timing pattern data and the output pattern data of FIFO1 are full FLA bit 1 the write operation becomes invalid an interrupt is generated th...

Page 683: ...FIFO1 Pointer Clear CLRA Clears the FIFO1 write position pointer After 1 is written the bit immediately reverts to 0 Writing 0 in this bit has no effect Bit 0 CLRA Description 0 Normal operation Init...

Page 684: ...or to free running counter Bit 7 FRT Description 0 5 bit DFG counter 16 bit timer counter Initial value 1 16 bit FRC Bit 6 FRG2 Clear Stop Bit FGR2OFF Nullifies the clearing of the counter by the DFG...

Page 685: ...f FIFO1 FIFO2 or only 10 stages of FIFO1 are used If 20 stage output mode is used in single mode data write in FIFO1 and FIFO2 is required Monitor the output FIFO group flag OFG and control it by soft...

Page 686: ...11 00 page 659 of 1037 Bit 0 Output Switching Bit Between VideoFF and NarrowFF VFF NFF Switches the signal output to the VideoFF pin Bit 0 VFF NFF Description 0 VideoFF output Initial value 1 NarrowFF...

Page 687: ...determined HSLP sets the number of the loop stages when the HSW timing generator is in loop mode It is valid if bit 5 LOP of HSM2 is 1 Bits 7 to 4 set the number of FIFO2 stages Bits 3 to 0 set the nu...

Page 688: ...Initial value 0 Only 0th stage of FIFO2 is output 0 1 0th and 1st stages of FIFO2 are output 0 0th to 2nd stages of FIFO2 are output 0 1 1 0th to 3rd stages of FIFO2 are output 0 0th to 4th stages of...

Page 689: ...Initial value 0 Only 0th stage of FIFO1 is output 0 1 0th and 1st stages of FIFO1 are output 0 0th to 2nd stages of FIFO1 are output 0 1 1 0th to 3rd stages of FIFO1 are output 0 0th to 4th stages of...

Page 690: ...access is valid If a byte access is attempted resulting operation is not assured No read is valid If a read is attempted an undetermined value is read out It is not initialized by a reset stand by or...

Page 691: ...is written at the same time to the position pointed by the buffer pointer of FIFO2 Be sure to write the output pattern data in FPDRB before writing it in FTPRB FPDRB is a 16 bit write only register O...

Page 692: ...0 FTPRA9 FTPRA8 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0 1 0 3 2 5 4 7 W 6 W 9 W 8 W 11 W 10 W W W W W W W W 12 Bit Initial value R W Note Undetermined FTPRA is a register to write the...

Page 693: ...dingly be sure to write data before use 8 DFG Reference Register 1 DFCRA 0 1 W 2 W 3 4 W 0 W 5 6 0 7 DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0 0 W ISEL2 W W W CCLR CKSL Bit Initial value R W Note Undetermine...

Page 694: ...e after a reset or stand by It is valid only if bit 7 FRT bit of HSM2 is 0 9 DFG Reference Register 2 DFCRB 0 1 W 2 W 3 4 W 5 6 1 7 DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0 W W 1 1 Bit Initial value R W Not...

Page 695: ...ration is not assured It is initialized to H 0000 by a reset or stand by Note Its address is shared with the FIFO timing pattern register 1 FTPRA Accordingly if a write is attempted the value is writt...

Page 696: ...as the timing patterns for FIFO1 and FIFO2 Free run Mode Free run mode is to operate together with the prescaler unit An overflow of the 18 bit free running counter in the prescaler unit initializes...

Page 697: ...e is active data can be rewritten for each FIFO group After confirming with the OFG bit of the HSW mode register 2 which FIFO group is outputting clear the FIFO group which is not outputting and write...

Page 698: ...1037 DPG 0 1 tA1 tA2 tB1 tA3 tA1 2 3 4 5 6 7 8 9 10 11 0 1 2 V FF A FF Clear A Clear B Example of setting DFCRA H 02 DFCRB H 08 HSLP H 21 DFG falling edge DFG Figure 28 23 Example of Timing Waveform o...

Page 699: ...O2 tB0 PB9 tB5 PB4 tB4 PB3 tB3 PB2 tB2 PB1 tB1 PB0 W W FPDRA Output select buffer Output select buffer Comparator FTPRA FIFO1 tA0 PA9 tA5 PA4 tA4 PA3 tA3 PA2 tA2 PA1 tA1 PA0 Internal bus FPDRB Timer c...

Page 700: ...PA0 d Repeat the steps in the same way until PA1 PA2 etc are set e Write the output pattern data PB0 to FPDRB f Write the output timing tB1 to FTPRB tB1 is written in FIFO2 together with PB0 This ini...

Page 701: ...ializes the output pattern data to PA0 d Repeat the steps in the same way until PA1 PA2 etc are set e Write the output pattern data PB0 to FPDRB f Write the output timing tB1 to FTPRB tB1 is written i...

Page 702: ...IRRHSW1 occurred when matching was detected and the STRIG bit of FIFO was 1 3 IRRHSW1 occurred when the values of the 16 bit timer counter and 16 bit timing pattern register matched 4 IRRHSW2 occurre...

Page 703: ...the rising edge of DPG and DFG count edge at different timings If the same timing was input counting up of DFG and clearing of the 5 bit DFG counter occurs simultaneously In this case the latter will...

Page 704: ...se bars the C Rotary and H Amp SW signals are synchronized to the horizontal sync signal OSCH OSCH is made by adding supplemented H which has been separated from the Csync signal in the sync signal de...

Page 705: ...ut Input of pre amplifier output result signal Color rotary signal output pin C Rotary Output Output of chroma processing control signal Head amplifier switching pin H Amp SW Output Output of pre ampl...

Page 706: ...nitialized to H 00 by a reset stand by or module stop Bit 7 HSW Signal Selection Bit V N Selects the HSW signal to be used at special playback Bit 7 V N Description 0 Video FF signal output Initial va...

Page 707: ...Bits 3 to 0 Signal Control Bits SIG3 to SIG0 These bits combined with the state of the COMP input pin control the outputs at the C Rotary and H Amp SW pins Bit 3 Bit 2 Bit 1 Bit 0 Output Pins SIG3 SIG...

Page 708: ...tor as the DFG signal The speed error detector uses the system clock to measure the period of the DFG signal and detects the deviation from a preset data value The preset data is the value that would...

Page 709: ...R W W R W R W R W R W R W Rock 1 up S R F F Q S R F F DFRCS1 0 DF R UNR Lock counter 2 bits Q S R F F Q Lock range detector Lock range data 1 16bit DPCNT Error data limitter control circuit DFEFON DFE...

Page 710: ...ration Name Abbrev R W Size Initial Value Address Specified DFG speed preset data register DFPR W Word H 0000 H FD030 DFG speed error data register DFER R W Word H 0000 H FD032 DFG lock UPPER data reg...

Page 711: ...ed DFG speed preset data H 8000 2 DFG frequency s Servo clock frequency fosc 2 in Hz DFG frequency In Hz The constant 2 is the presetting interval see Figure 28 28 s n Clock source of selected counter...

Page 712: ...3 2 5 4 7 1 W 6 1 W 9 1 W 8 1 W 11 1 W 10 1 W 1 W W W W W W W 12 1 1 1 1 1 1 Bit Initial value R W DFRUDR is a register used to set the lock range on the UPPER side when drum speed lock is detected a...

Page 713: ...be controlled automatically Also if the DFG speed error data is under the DFRLDR value when the limiter function is in use the DFRLDR value can be used as the data for computation by the digital filte...

Page 714: ...write occurs simultaneously the latter is nullified Bit 5 DFOVF Description 0 Normal state Initial value 1 Indicates that overflow has occurred in the counter Bit 4 Error Data Limit Function Selectio...

Page 715: ...et by the lock range data register It sets the drum lock flag if it detected the set number of times of occurrence of drum lock If an NCDFG signal is detected outside the lock range after data is writ...

Page 716: ...R value is sent if a negative number is latched or the DFRUDR value is sent if a positive one is latched as a limit value Be sure to turn off the limit setting DFRFON 0 when you set the limit value If...

Page 717: ...is generated by detection of lock after the detection of the number of times of setting value value Specified speed value Latch data 0 no error Preset value Preset period 2 counts Counter NCDFG signal...

Page 718: ...rizontal sync frequency To shift the drum motor speed software should modify the value written in the DFG preset data register in the speed error detector This fH correction can be expressed in terms...

Page 719: ...ed PWM output which controls the rotational phase and speed of the drum The DPG signal from the drum motor is reshaped into a rectangular pulse waveform by a reshaping circuit and sent to the phase er...

Page 720: ...F F Q W W Internal bus Internal bus OVF LSB MSB DPER1 DPER2 LSB MSB DPOVF DFEPS HSWES N V Latch Preset Error data 20 bits To DFU Edge detector Sequence controller Error data 16bit Error data 4bit Pres...

Page 721: ...ration Name Abbrev R W Size Initial Value Address Drum phase preset data register 1 DPPR1 W Byte H F0 H FD03C Drum phase preset data register 2 DPPR2 W Word H 0000 H FD03A Drum phase error data regist...

Page 722: ...set circuit Write to DPPR1 first and DPPR2 next The preset data is referenced to H 80000 and can be calculated from the following equation Target phase difference reference signal frequency 2 6 5H Dru...

Page 723: ...t 3 of DPER1 is the MSB and bit 0 of DPER2 is the LSB When the rotational phase is correct the data H 00000 is latched Negative data will be latched if the drum leads the correct phase and positive da...

Page 724: ...zed to H 07 by a reset or stand by Bits 7 and 6 Clock Source Selection Bits DPCS1 DPCS0 Select the clock supplied to the counter s fosc 2 Bit 7 Bit 6 DPCS1 DPCS0 Description 0 s Initial value 0 1 s 2...

Page 725: ...data detected in the error data automatic transmission mode DFEPS bit of DFUCR 0 is sent to the digital filter circuit automatically In software transmission mode DFEPS bit of DFUCR 1 the data writte...

Page 726: ...Preset Note Edge selectable Preset Figure 28 30 Drum Phase Control in Playback Mode HSW Rising Edge Selected Latch Latch Preset value Counter HSW NHSW VD REF30P Preset value Preset Note Edge selectabl...

Page 727: ...EF30 signal is the same as that of the vertical sync signal Vsync because the reference signal generator REF30 generator is reset by the vertical sync signal Vsync in the video signals The error detec...

Page 728: ...and sent to the speed error detector as the DVCFG signal The speed error detector uses the system clock to measure the period of the DVCFG signal and detects the deviation from a preset data value Th...

Page 729: ...R W W R W R W R W R W R W Lock 1 up S R F F Q S R F F CFRCS1 0 CF R UNR Lock counter 2 bits Q S R F F Q Lock range detector Lock range data 2 16 bits Lock range data 1 16 bits CPCNT Error data limitt...

Page 730: ...onfiguration Name Abbrev R W Size Initial Value Address CFG speed preset data register CFPR W Word H 0000 H FD050 CFG speed error data register CFER R W Word H 0000 H FD052 CFG lock UPPER data registe...

Page 731: ...clock frequency in Hz fOSC 2 DVCFG frequency In Hz The constant 2 is the preset interval see figure 28 33 s n Clock source of the selected counter CFPR is a 16 bit write only register CFPR is accessib...

Page 732: ...W 15 1 0 3 2 5 4 7 1 W 6 1 W 9 1 W 8 1 W 11 1 W 10 1 W 1 W W W W W W W 12 1 1 1 1 1 1 Bit Initial value R W CFRUDR is a register used to set the lock range on the UPPER side when capstan speed lock i...

Page 733: ...value can be used as the data for computation by the digital filter CFRLDR is a 16 bit write only register Only a word access is valid If a byte access is attempted operation is not assured No read i...

Page 734: ...lock range data register CFRUDR CFRLDR Bit 4 CFRFON Description 0 Limit function off Initial value 1 Limit function on Bit 3 Capstan Lock Flag CF R UNR Sets a flag if an underflow occurred in the cap...

Page 735: ...set in the CFG speed preset register CFPR The reference value set in CFPR is preset in the counter by the DVCFG signal and counts down by the selected clock The timing of the counter presetting and th...

Page 736: ...utation can be controlled automatically by the status of lock detection c Capstan system speed error detection counter The capstan system speed error detection counter stops the counter and sets the o...

Page 737: ...r data is processed and added by the digital filter circuit to control the PWM output The phase and speed of the capstan in turn is controlled by this PWM output The control signal of the capstan phas...

Page 738: ...SB MSB CPER1 CPER2 LSB MSB CPOVF CFEPS SELCFG2 R W CTLM R P ASM Latch Preset Error data 20 bits To DFU Sequence controller Error data 16 bit Error data 4 bit Preset data 16 bit Preset PB X value TRK v...

Page 739: ...Name Abbrev R W Size Initial Value Address Capstan phase preset data register 1 CPPR1 W Byte H F0 H FD05C Capstan phase preset data register 2 CPPR2 W Word H 0000 H FD05A Capstan phase error data reg...

Page 740: ...CPPR2 next The preset data is referenced to H 80000 and can be calculated from the following equation Target phase difference Rreference signal frequency 2 Capstan phase preset data H 80000 s n targe...

Page 741: ...3 of CPER1 is the MSB Bit 0 of CPER2 is the LSB When the rotational phase is correct the data H 00000 is latched Negative data will be latched if the phase leads the correct phase and positive data if...

Page 742: ...nitialized to H 07 by a reset or stand by Bits 7 and 6 Clock Source Selection Bits CPCS1 CPCS0 Select the clock supplied to the counter s fosc 2 Bit 7 Bit 6 CPCS1 CPCS0 Description 0 s Initial value 0...

Page 743: ...p by the clock selected The latching of the error data is performed by DVCTL or DVCFG2 The error data detected in the error data automatic transmission mode CFEPS bit of DFUCR 0 is sent to the digital...

Page 744: ...atch and the overflow of the error detection counter Latch Latch Preset value Counter PB CTL CAPREF30 DVCTL or DVCFG2 Preset Preset Figure 28 35 Capstan Phase Control in Playback Mode Latch Latch Pres...

Page 745: ...l alignment tracking alignment of the video head with the recorded tracks in autotracking or when tracks that were recorded with an EP head are traced by a wider head These tracking adjustments can be...

Page 746: ...CR W W XCS XTCR W AT MU ASM REC PB XTCR W TRK X S R Q S R Q Internal bus Internal bus DVREF1 0 CAPRF EXC REF W W XTCR XTCR Down counter Edge selection 2bit Counter 10bit CAPREF30 REF30X W X value data...

Page 747: ...DVREF0 1 Bit Initial value R W XTCR is an 8 bit register to determine the X value and TRK value adjustment circuits Bits 6 to 2 are write only bits No read is valid If a read is attempted an undeterm...

Page 748: ...RK Determines the method to generate the CAPREF30 signal when the AT 08 bit is 0 Bit 4 TRK Description 0 Generates CAPREF30 only by the set value of XDR Initial value 1 Generates CAPREF30 by the set v...

Page 749: ...s attempted operation is not assured Set X value correction data to XDR except a value which is beyond the cycle of the CTL pulse If AT 08 0 TRK 0 was set CAPREF30 can be generated only by the setting...

Page 750: ...multiplier accumulator an arithmetic buffer and an I O processor The digital filter computations are carried out by the high speed multiplier accumulator The arithmetic buffer stores coefficients and...

Page 751: ...gister select R W Address bus Error check Accumulation controller LA 16 bits lower accumulator UA 32 bits upper accumulator MD 32 bits multiplied data Data shifter Accumulation sequence circuit Buffer...

Page 752: ...M Digital filter control register Speed system 24 8 Z 1 Upn 1 GKp OfP 24 8 Tp 24 8 VBp 24 8 XAp 24 8 VPn 24 8 Y Phase direct test output See figure 28 42 Z 1 initialization circuit 12 24 8 Ep Error de...

Page 753: ...ata is used by hardware None of the data can be read Table 28 14 Arithmetic Buffer Register Configuration Buffer Data Length Arithmetic Data Gain or Coefficient Processing Data 16 bits 16 bits 16 bits...

Page 754: ...p W Word Undetermined H FD000 Drum speed gain constant DGKs W Word Undetermined H FD002 Drum phase coefficient A DAp W Word Undetermined H FD004 Drum phase coefficient B DBp W Word Undetermined H FD00...

Page 755: ...ocessing starts In the digital filter output gain and accumulation gain can be adjusted separately Take output gain into account when setting accumulation gain 2 Coefficients DAp DBp DAs DBs CAp CBp C...

Page 756: ...accumulation gain 4 Delay Initialization Registers CZp CZs DZp DZs 13 14 15 1 0 3 2 5 4 7 0 W 6 0 W 9 0 W 8 0 W 11 0 W 10 0 W W W W W W W 12 0 0 0 0 0 0 1 1 1 1 Bit Initial value R W The delay initial...

Page 757: ...by a reset and in standby mode and module stop mode Bit 7 Reserved Reads and writes are both disabled Bit 6 Drum System Range Over Flag DROV This flag is set to 1 when the result of a drum system fil...

Page 758: ...Drum Speed System Z 1 Initialization Bit DZSON Reflects the DZs value on Z 1 of the speed system when computation processing of the drum speed system begins If 1 was written it is reflected on the com...

Page 759: ...ed to H 80 by a reset and in standby mode and module stop mode Bit 7 Reserved Reads and writes are both disabled Bit 6 Capstan System Range Over Flag CROV This flag is set to 1 when the result of a ca...

Page 760: ...3 Capstan Speed System Z 1 Initialization Bit CZSON Reflects the CZs value on Z 1 of the capstan speed system when computation processing of the speed system begins If 1 was written it is reflected on...

Page 761: ...ult PWM Output Bit PTON Outputs the computation results of only the phase system to PWM The computation results of the drum phase system is output to the CAPPWM pin and that of the capstan phase syste...

Page 762: ...or data is transferred by HSW NHSW signal latching Initial value 1 Error data is transferred when the data is written Bit 1 Capstan Speed System Error Data Transfer Bit CFESS Transfers the capstan spe...

Page 763: ...mpulse Response type digital filter another type of the digital filter is FIR i e Finite Impulse Response type This digital filter circuit implements a lag lead filter as shown in figure 28 40 R1 R2 C...

Page 764: ...hows the frequency characteristics of the lag lead filter f1 0 f2 Frequency Hz 20log f1 f2 gain dB phase deg Figure 28 41 Frequency Characteristics of the Lag Lead Filter The pulse transfer function G...

Page 765: ...Z 1 can be initialized by its delay initialization register CZp CZs DZp DZs Loading to Z 1 is performed automatically by bits 4 and 3 of CFIC and DFIC CZPON CZSON DZPON DZSON Writing in register is al...

Page 766: ...ay initialization register Z 1 USn Res Note MSB of 12 bit data to be written in the delay initialization register is a sign bit Usn 1 Xn Vn DBs15 to 0 DBp15 to 0 CBs15 to 0 CBp15 to 0 DZs11 to 0 DZp11...

Page 767: ...l V signal control circuit Csync Additional V pulse OSCH Vpulse signal Mlevel signal Sync detector HSW timing generator Additional V pulse generator Figure 28 43 Additional V Pulse Control Circuit a H...

Page 768: ...signal Table 28 17 Register Configuration Name Abbrev R W Size Initial Value Address Additional V control register ADDVR R W Byte H E0 H FD06F 28 12 4 Register Description Additional V Control Registe...

Page 769: ...is a three level output pin Initial value 1 Vpulse is a three state output pin high low or high impedance Bits 2 to 0 Additional V Output Control Bit CUT VPON POL These bits control the output at the...

Page 770: ...s The polarity can be selected by the POL bit in the additional V register ADDVR The Vpulse pin outputs a low level by a reset and in standby mode and module stop mode R W R W ADDVR ADDVR R W Internal...

Page 771: ...sed In this case there may be slight timing drift compared with the normal sync signal depending on the HRTR and FPWR setting with resultant discontinuity If no sync signal is input the additional V p...

Page 772: ...Rev 2 0 11 00 page 745 of 1037 HSW signal edge OSCH VPON 1 CUT 0 POL 0 Additional V pulse Vpulse signal Mlevel signal Figure 28 46 Additional V Pulse When Negative Polarity is Specified...

Page 773: ...TL circuit that detects and records VISS ASM and VASS marks A REC CTL amplifier is included in the record circuits Detection and recording whether the CTL pulse pattern is long or short can also be en...

Page 774: ...of the CTL circuit PB CTL FW RV CTL CTL Schmitt amplifier CTL mode CTL detector Duty des criminator Bit pattern register VISS detect VISS control circuit VISS write Duty I O flag Write control circuit...

Page 775: ...control CTL REF output pin CTL REF Output CTL amplifier reference voltage output 28 13 4 Register Configuration Table 28 19 shows the register configuration of the CTL circuit Table 28 19 Register Con...

Page 776: ...is detected CTCR is an 8 bit readable writable register However bit 1 is read only and the rest is write only CTCR is initialized to H 30 by a reset and in standby and module stop mode Bit 7 NTSC PAL...

Page 777: ...at the setting value Initial value 1 Clock source CCS operates for further 8 division after operating at the setting value Bit 1 CTL Undetected Bit UNCTL Indicates the CTL pulse detection status at t...

Page 778: ...is being stopped only bits 7 6 and 5 operate Note Do not set any value other than the setting value for each mode see table 28 20 CTL Mode Functions Bits 7 and 6 Record Playback Mode Bits ASM REC PB T...

Page 779: ...ASM REC 3 3 FW RV MD4 MD3 MD2 MD1 MD0 Mode Description 0 0 0 1 0 0 0 0 0 VASS detect duty detect PB CTL duty discrimination Initial value Duty I O flag is set to 1 if duty 44 is detected Duty I O flag...

Page 780: ...ata with 0 pulse data at both edges are written index record The index bit string is written through the duty I O flag An interrupt request is generated at the end of VISS recording 0 0 0 0 0 1 0 1 VI...

Page 781: ...esults If read is attempted an undetermined value is read out Bits 15 to 12 are reserved and are not affected by write access RCDR1 is initialized to H F000 by a reset and in standby mode module stop...

Page 782: ...e is read out Bits 15 to 12 are reserved and are not affected by write access RCDR2 is initialized to H F000 by a reset and in standby mode module stop mode and CTL stop mode At recording the value to...

Page 783: ...e not affected by write access RCDR3 is initialized to H F000 by a reset and in standby mode module stop mode and CTL stop mode At recording the value to set in RCDR3 can be calculated from the transi...

Page 784: ...ssured If a read is attempted an undefined value is read out Bits 15 to 12 are reserved and no write in them is valid It is initialized to H F000 by a reset stand by module stop or CTL stop In record...

Page 785: ...ssured If a read is attempted an undefined value is read out Bits 15 to 12 are reserved and no write in them is valid It is initialized to H F000 by a reset stand by module stop or CTL stop In record...

Page 786: ...SS Interrupt Setting Bits VCTR2 VCTR1 VCTR0 Combination of VCTR2 VCTR1 and VCTR0 sets number of 1 pulse detection in VISS detection mode Detecting the set number of pulse detection is considered as VI...

Page 787: ...e flag every time 8 bit PB CTL is detected in PB or ASM mode To clear the flag write 0 after reading 1 Bit 1 BPF Description 0 Bit pattern 8 bit is not detected Initial value 1 Bit pattern 8 bit is de...

Page 788: ...pulse long in RCDR5 While an index code is being written the value of the bit being written can be read by reading the duty I O flag If the CTL signal currently being written is a 0 pulse the duty I...

Page 789: ...B mode the register starts detection of bit pattern immediately after the CTL pulse To exit the bit pattern detection set the BPON bit at 0 If 1 was written in the BPS bit when the bit pattern is bein...

Page 790: ...ch detection Match detection Match detection Match detection RCDR1 12 bit register UDF DOWN UDF Upper 12 bits UP UP DOWN counter 16 bits Duty detection Counter clear signal REF30X REC PB CTL PB ASM UP...

Page 791: ...UDF 0 pulse 0 pulse CDIVR2 Register write Ta is the interval calculated from RDCR3 Tb is the interval in which switchover is performed from ASM mode to REC mode Tx is the cycle in which the REF30X pe...

Page 792: ...ed from RDCR3 Tb is the interval in which switchover is performed from ASM mode to REC mode Tx is the cycle in which the REF30X period is shortened due to the change of XDR With CREF and DVCFG2 phase...

Page 793: ...head amplified by the input amplifier reshaped into a square wave by the Schmitt amplifier and sent to the servo circuits and timer L as the PB CTL signal Control the CTL input amplifier gain by bits...

Page 794: ...ypically detection or non detection is determined within 3 to 4 cycles of the reference period If settings of the CTL gain control register are maintained in a table format you can refer to it when th...

Page 795: ...reset The time TFS s until the signal falls is the following interval after the rising edge of the internal CTL signal is detected TFS 16384 4 s s fOSC 2 When fOSC 10 MHz TFS 13 1 ms Figure 28 54 show...

Page 796: ...l to or above 66 When the duty cycle is below 65 no ASM mark is recognized and the duty I O flag is set to 1 The detection direction can be switched between forward and reverse by bit 5 FW RV in the C...

Page 797: ...signal Short 1 pulse 25 0 5 PB CTL Input signal Long 1 pulse 30 0 5 PB CTL Input signal Short 0 pulse 57 5 0 5 62 5 0 5 PB CTL Input signal Long 0 pulse PB CTL Input signal ASM Mark 67 to 70 PB CTL F...

Page 798: ...to RCDR5 Counter PB CTL 1 pulse PB CTL PB CTL s 4 s 5 Counter PB CTL 0 pulse s 4 s 5 Counter FWD PB CTL Short pulse 0 pulse s 4 s 5 RCDR3 RCDR2 0 pulse L S threshold value 1 pulse L S threshold value...

Page 799: ...ord or rewrite INDEX code is automatically written INDEX code is composed of continuous 62 bit data with 0 pulse data at both edges Examples of bit strings and the duty I O flag at VISS detection reco...

Page 800: ...ead by the interrupt handling routine within the period of the PB CTL signal The VASS detection format is illustrated in figure 28 58 1 Tape direction Written three times 1 1 1 1 1 1 1 1 1 1 M S B L S...

Page 801: ...eshold of 0 pulse L S for FWD to RCDR4 a threshold of 0 pulse L S for REV and to RCDR5 a threshold of 1 pulse L S for REV Figure 28 59 shows the detection of the Long Short pulse Also the bit pattern...

Page 802: ...tten in the duty I O flag the REC CTL signal will be written on the tape with a 25 0 5 duty cycle when 0 is written in bit 7 LSP7 in the bit pattern register BTPR and with a 30 0 5 duty cycle when 1 i...

Page 803: ...End of writing of one CTL pulse except VISS IRRCTL RCDR2 VISS VASS S1 pulse RCDR3 VISS VASS L1 pulse or ASM RCDR4 VISS VASS S0 pulse RCDR5 VISS VASS L0 pulse RCDR1 Clear Upper 12 bits REC CTL 0 pulse...

Page 804: ...DR5 can be written to by software at all times If RCDR is changed before the respective match detection is performed match detection is performed using the new value The value changed after match dete...

Page 805: ...nced to the rise of PB CTL Figure 28 62 shows the rewrite waveform W Internal bus RCDR3or5 12bit W Not used when rewriting RCDR2or4 12bit UP DOWN counter 16 bits Clear Upper 12 bits REC CTL 0 pulse fa...

Page 806: ...lowing a reset the CTL circuit is in the VASS detect duty detect mode Depending on the CTL pin states a false PB CTL input pulse may be recognized and an interrupt request generated If the interrupt r...

Page 807: ...ided signals DVCFG for speed control and DVCFG2 for phase control from the CFG signal The DFG noise canceller is a circuit which considers a signal less than 2 as noise and masks it 28 14 2 CTL Freque...

Page 808: ...nal input signal is used to generate the DVCTL signal Bit 7 CEX Description 0 Generates DVCTL signal with PB CTL signal Initial value 1 Generates DVCTL signal with external input signal Bit 6 External...

Page 809: ...l CTL frequency division register CTLR 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 6 0 7 CTL4 CTL3 CTL2 CTL1 CTL0 0 W CTL7 W W W CTL6 CTL5 Bit Initial value R W The CTL frequency division register CTLR is an 8 bi...

Page 810: ...circuits and the Timer R The CTL frequency divider is an 8 bit reload timer consisting of a reload register and a down counter Frequency division is obtained by setting frequency division data in bits...

Page 811: ...its mask timer W R W W R W W W W R R W Internal bus CMN CRF UDF UDF UDF CFG DVCFG DVCFG2 MCGin Internal bus CFG clock select CTMR 6bit CDIVR2 7bit DVTRG PB ASM REC s fosc 2 s 1024 s 512 s 256 s 128 D...

Page 812: ...RF CPS1 CPS0 0 Note Only 0 can be written Bit Initial value R W CDVC is an 8 bit register to control the capstan frequency division circuit It is initialized to H 60 by a reset stand by or module stop...

Page 813: ...apstan mask timer function ON Initial value 1 Capstan mask timer function OFF Bit 3 PB ASM REC Transition Timing Sync ON OFF Selection Bit DVTRG Selects the ON OFF of the timing sync of the transition...

Page 814: ...ge 787 of 1037 Bits 1 and 0 CFG Mask Timer Clock Selection Bits CPS1 CPS0 Selects the clock source for the CFG mask timer s fosc 2 Bit 1 Bit 0 CPS1 CPS0 Description 0 s 1024 Initial value 0 1 s 512 0...

Page 815: ...V25 CDV24 0 W CDV26 0 W CDV23 CDV22 CDV21 CDV20 1 Bit Initial value R W The CFG frequency division register 2 CDIVR2 is an 8 bit write only register to set the CFG division value N 1 for N division If...

Page 816: ...divider with a mask timer for capstan speed control DVCFG signal generator and a 7 bit frequency divider for capstan phase control DVCFG2 signal generator The DVCFG signal generator consists of a 7 bi...

Page 817: ...er CPGCR If synchronization is necessary for phase control this can be provided by writing the frequency division value in CDIVR2 The down counters are decremented on rising edges of the CFG signal wh...

Page 818: ...ain period The above trouble can result from abnormal revolution runout of the capstan motor because its revolution has to cover a wide range speeds from the slow still up to the high speed search The...

Page 819: ...Cleared by writing 0 after reading 1 Capstan motor mask timer Mask interval Mask interval DVCFG MCGin flag Figure 28 68 CFG Mask Timer Operation When Capstan Motor is Racing CFG Edge detect Capstan mo...

Page 820: ...ddress FG control register FGCR W Byte H FE H FD09E FG Control Register FGCR 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 W DRF 1 Bit Initial value R W Selects the edge of the DFG noise removal signal NCDFG to be se...

Page 821: ...lue 1 Selects the falling edge of NCDFG signal 3 Description of Operation The DFG noise removal circuits generates a signal NCDFG signal with a delay circuit as a result of removing noise signal fluct...

Page 822: ...setting threshold in the register and based on the servo clock s fosc 2 Noise masking is possible during the detection of the horizontal sync signals and if any Hsync is missing it can be supplemented...

Page 823: ...R W R NOIS H counter 8 bit Noise detector Supplement control noise mask control circuit Up Down counter 6 bit SEPH Selection of polarity Noise detection window Noise detection interrupt VD interrupt C...

Page 824: ...sync signal detector Table 28 26 Register Configuration Name Abbrev R W Size Initial Value Address Vertical sync signal threshold register VTR W Byte H C0 H FD0B0 Horizontal sync signal threshold reg...

Page 825: ...VTR1 VTR0 1 Bit Initial value R W Sets the threshold for the vertical sync signal when the signal is detected from the composite sync signal The threshold is set by bits 5 to 0 VTR5 to VTR0 Bits 7 and...

Page 826: ...ined value is read out It is initialized to H F0 by a reset stand by or module stop Figure 28 73 shows threshold and separated sync signals Legend TH Hpuls TH SEPV Hpuls Cycle of the horizontal sync s...

Page 827: ...VTH VVTH 1 2 s Hpuls HVTH 2 2 s Hpuls 2 HVTH 1 2 s Where Hpuls is pulse width s of the horizontal sync signal and s is servo clock fosc 2 Thus if s 5 MHz NTSC system is used VVTH 1 0 4 s 4 7 s VVTH H...

Page 828: ...cordingly set to HRTR7 to HRTR0 a value obtained from the equation shown above plus one Also HRTR7 to HRTR0 set the noise mask period If the horizontal sync signal had the normal pulses it is masked i...

Page 829: ...cycle of the horizontal sync signal 6 Noise Detection Register NDR 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 6 0 7 NDR4 NDR3 NDR2 NDR1 NDR0 0 W NDR7 W W W NDR6 NDR5 Bit Initial value R W NDR sets the noise dete...

Page 830: ...etermined value is read out Bit 3 Interrupt Selection Bit NIS VD Selects whether an interrupt request is generated when a noise level was detected or when the VD signal was detected Bit 3 NIS VD Descr...

Page 831: ...currently being scanned is even or odd See figure 28 74 Bit 1 FLD Description 0 Odd field Initial value 1 Even field Bit 0 Sync Signal Polarity Selection Bit SYCT Selects the polarity of the sync sig...

Page 832: ...etection flag FLD SEPV Noise detection window Composite sync signal Csync Even field a Even field EVEN Field detection flag FLD SEPV Noise detection window Composite sync signal Csync Odd field b Odd...

Page 833: ...e timing HRTR7 0 supplemented pulse width HPWR3 0 and noise detection window timing NWR5 0 are expressed by the following equations Value of HRTR7 0 2 s TH Value of HPWR3 0 1 2 s Hpuls Value of NWR5 0...

Page 834: ...noise mask period The noise mask period ends 24 counts before the overflow of H reload counter Cycle of the horizontal sync signal NTSC 63 6 ms PAL 64 ms TM Timing at which the noise mask period ends...

Page 835: ...rame Vsync is detected twice The equivalent pulse contained in 9H of the vertical sync signal is counted also as an irregular pulse It sets the noise detection flag NOIS in the sync signal control reg...

Page 836: ...SYCT bit of the sync signal control register SYNCR The detector starts operation even if this pulse was a noise pulse with a width short of the regular width The minimum pulse width which can activat...

Page 837: ...28 27 Registers which Control the Interrupt of the Servo Section Name Abbrev R W Size Initial Value Address Servo interrupt permission register 1 SIENR1 R W Byte H 00 H FD0B8 Servo interrupt permissio...

Page 838: ...RRDRM2 Bit 5 Drum Speed Error Detection OVF latch Interrupt Permission Bit IEDRM1 Bit 5 IEDRM1 Description 0 Prohibits the interrupt request through IRRDRM1 Initial value 1 Permits the interrupt reque...

Page 839: ...RCAP1 Bit 1 HSW Timing Generation counter clear capture Interrupt Permission bit IEHSW2 Bit 1 IEHSW2 Description 0 Prohibits the interrupt request through IRRHSW2 Initial value 1 Permits the interrupt...

Page 840: ...by or module stop Bits 7 to 2 Reserved No read or write is valid If a read is attempted an undetermined value is read out Bit 1 Vertical Sync Signal Interrupt Permission Bit IESNC Bit 1 IESNC Descript...

Page 841: ...reset stand by or module stop Bit 7 Drum Phase Error Detector Interrupt Request Bit IRRDRM3 Bit 7 IRRDRM3 Description 0 No interrupt request from the drum phase error detector Initial value 1 Interru...

Page 842: ...or OVF latch Interrupt Request Bit IRRCAP1 Bit 2 IRRCAP1 Description 0 No interrupt request from the capstan speed error detector OVF latch Initial value 1 Interrupt requested from the capstan speed e...

Page 843: ...ng 0 after reading 1 is allowed no other writing is allowed It is initialized to H FC by a reset stand by or module stop Bits 7 to 2 Reserved No read or write is valid If a read is attempted an undete...

Page 844: ...bit readable writable registers that perform module stop mode control When the MSTP1 bit is set to 1 servo circuit and 12 bit PWM stop the operation at the end of the bus cycle and enter to the modul...

Page 845: ...Rev 2 0 11 00 page 818 of 1037...

Page 846: ...A D converter input voltage AVin 0 3 to AVcc 0 3 V Servo power supply voltage SVcc 0 3 to 7 0 V Servo amplifier input voltage Vin 0 3 to SVcc 0 3 V Operating temperature Topr 20 to 75 C Operating temp...

Page 847: ...le Pins Test Conditions Min Typ Max Unit Notes MD0 Vcc 2 7 to 5 5V 0 9 Vcc Vcc 0 3 0 8 Vcc Vcc 0 3 5 6 10 FWE 54 to 54 Vcc 2 7 to 5 5V 0 9 Vcc Vcc 0 3 SCK1 SCK2 SI1 SI2 6 FTIA FTIB FTIC FTID TRIG TMBI...

Page 848: ...3 0 3 Vcc P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 PS0 to PS4 Vcc 2 7 to 5 5V 0 3 0 2 Vcc Input low voltage VIL Csync 0 3 0 2 Vcc V IOH 1 0mA...

Page 849: ...P70 to P77 PS0 to PS4 IOL 0 4mA Vcc 2 7 to 5 5V 0 4 V IOL 20mA 1 5 V IOL 1 6mA 0 6 V Output low voltage VOL P80 to P87 IOL 0 4mA Vcc 2 7 to 5 5V 0 4 V MD0 OSC1 5 6 10 FWE 54 to 54 Vin 0 5 to Vcc 0 5V...

Page 850: ...a tion CPU operating IOPE Vcc Vcc 5V fOSC 10 MHz Medium speed mode 1 64 35 mA Refer ence value Active mode current dissipa tion reset IRES Vcc Vcc 5V fOSC 10 MHz 30 45 mA Note 2 Sleep mode current dis...

Page 851: ...t in use 1 Current value when the relevant bit of the pull up MOS select register PUR1 to PUR3 is set to 1 2 The current on the pull up MOS or the output buffer excluded Table 29 3 Pin Status at Curre...

Page 852: ...plicable pin SCL SDA Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes VT 0 2Vcc V VT 0 7Vcc V Schmidt trigger input voltage VT VT SCL SDA 0 05Vcc V Input High voltage VIH SCL...

Page 853: ...from chip IO 50 mA 6 Notes 1 The allowable input current is the maximum value of the current flowing from each I O pin to VSS except for port 8 SCL and SDA 2 The allowable input current is the maximu...

Page 854: ...me tsubcyc X1 X2 Vcc 2 7 to 5 5V 30 518 s Figure 29 2 OSC1 OSC2 Crystal oscillator 10 ms Oscillation stabilization time trc X1 X2 32kHz crystal oscillator Vcc 2 7 to 5 5V 2 s External clock high width...

Page 855: ...pin high level width tIH 54 to 54 10 75 TMBI FTIA FTIB FTIC FTID TRIG Vcc 2 7V to 5 5V 2 tcyc tsubcyc Input pin low level width tIL 54 to 54 10 75 TMBI FTIA FTIB FTIC FTID TRIG Vcc 2 7V to 5 5V 2 tcy...

Page 856: ...4 0V The tDEXT includes the RES pin Low level width 20 tcyc Note Figure 29 3 External Clock Stabilization Delay Timing RES VIL tREL Figure 29 4 Reset Input Timing tIL tIH VIH IRQ0 to IRQ5 NMI IC ADTRG...

Page 857: ...yc SCK2 2 tcyc Input clock pulse width tSCKW SCK1 SCK2 0 4 0 6 tscyc SCK1 1 5 tcyc Input clock rise time tSCKr SCK2 60 ns SCK1 1 5 tcyc Input clock fall time tSCKf SCK2 60 ns Figure 29 6 Transmit data...

Page 858: ...Kr VIL or VOL VIH or VOH SCK1 tSCKW tscyc Figure 29 6 SCK1 Clock Timing VIL VIH tTXD SCK1 SCK2 SO1 SO2 SI1 SI2 tRXS tRXH Figure 29 7 SCI I O Timing Clock Synchronization Mode VIH VIH VIL CS SCK2 tCSH...

Page 859: ...Rev 2 0 11 00 page 832 of 1037 LSI output pin Timing reference level VOH 2 0V VOL 0 8V 30pF 12k 2 4k Vcc Figure 29 9 Output Load Conditions...

Page 860: ...h tSCLL 5 tcyc SCL SDA input rise time tsr 7 5 1 tcyc SCL SDA input fall time tsf 300 ns SCL SDA input spike pulse removal time tsp 1 tcyc SDA input bus free time tBUF 5 tcyc Start condition input hol...

Page 861: ...H tSr tSDAH tSCL tSCLL tSCLH tSf tSTAS tSP tSTOS tSDAS VIL VIH SDA SCL P S Sr P S P and Sr denote the following S Start conditions P Stop conditions Sr Re transmit start conditions Note tBUF Figure 29...

Page 862: ...ply voltage AVcc AVcc Vcc 0 3 Vcc Vcc 0 3 V Analog input voltage AVIN AN0 to AN7 AN8 to ANB AVss AVcc V AICC AVcc AVcc 5 0V 2 0 mA Analog power supply current AISTOP AVcc Vcc 2 7 to 5 5V At reset and...

Page 863: ...GR2 1 CTLGR1 1 CTLGR0 0 f 10kHz 47 0 49 0 51 0 CTLGR3 0 CTLGR2 1 CTLGR1 1 CTLGR0 1 f 10kHz 49 5 51 5 53 5 CTLGR3 1 CTLGR2 0 CTLGR1 0 CTLGR0 0 f 10kHz 52 0 54 0 56 0 CTLGR3 1 CTLGR2 0 CTLGR1 0 CTLGR0 1...

Page 864: ...5 CFG input threshold voltage V THCF CFG Fall threshold level 2 75 V V THDF Rising edge Schmidt level 1 95 DFG Schmidt input V THDF DFG Falling edge Schmidt level 1 85 V V THDP Rising edge Schmidt lev...

Page 865: ...lues Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Note Digital input high voltage VIH 0 8 Vcc Vcc 0 3 Digital input low voltage VIL COMP EXCTL EXCAP EXTTRG 0 3 0 2 Vcc V Digital output...

Page 866: ...0 s Wait time after PSU bit clearing 1 10 s Wait time after PV bit setting 1 4 s Wait time after dummy write 1 2 s Wait time after PV bit clearing 1 4 s At programming Maximum No of programmings 1 4 5...

Page 867: ...ng N for maximum erasing time tE max is as follows tE max Wait time after E bit setting Maximum No of erasing N Set the z and N values so that they satisfy the above equation Ex When z 5 ms N 240 time...

Page 868: ...Vcc 4 0 to 5 5 V Vss AVss 0 0 V Ta 20 to 75 C unless otherwise specified Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes MD0 Vcc 2 5 to 5 5V 0 9 Vcc Vcc 0 3 0 8 Vcc Vcc 0 3 5...

Page 869: ...0 3 Vcc P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 PS0 to PS4 Vcc 2 5 to 5 5V 0 3 0 2 Vcc Input low voltage VIL Csync 0 3 0 2 Vcc V IOH 1 0mA Vc...

Page 870: ...7 P70 to P77 PS0 to PS4 IOL 0 4mA Vcc 2 5 to 5 5V 0 4 V IOL 20mA 1 5 V IOL 1 6mA 0 6 V Output low voltage VOL P80 to P87 IOL 0 4mA Vcc 2 5 to 5 5V 0 4 V MD0 OSC1 5 6 10 54 to 54 Vin 0 5 to Vcc 0 5V 1...

Page 871: ...CPU operating IOPE Vcc Vcc 5V fOSC 10 MHz Medium speed mode 1 64 35 mA Refer ence value Active mode current dissipa tion reset IRES Vcc Vcc 5V fOSC 10 MHz 25 45 mA Note 2 Sleep mode current dissipa t...

Page 872: ...not in use 1 Current value when the relevant bit of the pull up MOS select register PUR1 to PUR3 is set to 1 2 The current on the pull up MOS or the output buffer excluded Table 29 14 Pin Status at Cu...

Page 873: ...ess otherwise specified Applicable pin SCL SDA Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes VT 0 2 Vcc V VT 0 7 Vcc V Schmidt trigger input voltage VT VT SCL SDA 0 05 Vcc...

Page 874: ...wable input current to chip IO 80 mA 5 Total allowable output current from chip IO 50 mA 6 Notes 1 The allowable input current is the maximum value of the current flowing from each I O pin to VSS exce...

Page 875: ...SC2 100 125 ns Figure 29 11 Subclock oscillation frequency fX X1 X2 Vcc 2 5 to 5 5V 32 768 kHz Subclock cycle time tsubcyc X1 X2 Vcc 2 5 to 5 5V 30 518 s Figure 29 12 OSC1 OSC2 Crystal oscillator 10 m...

Page 876: ...2 5 to 5 5V 10 ns Figure 29 12 5 6 pin low level width tREL 5 6 Vcc 2 5V to 5 5V 20 tcyc Figure 29 14 Input pin high level width tIH 54 to 54 10 75 TMBI FTIA FTIB FTIC FTID TRIG Vcc 2 5V to 5 5V 2 tc...

Page 877: ...CLf tsubcyc tEXCLH tEXCLL tEXCLr VIL VIH X1 Vcc 0 5 Figure 29 12 Subclock Input Timing Vcc OSC1 tDEXT RES Internal 4 0V The tDEXT includes the RES pin Low level width 20 tcyc Note Figure 29 13 Externa...

Page 878: ...Rev 2 0 11 00 page 851 of 1037 RES VIL tREL Figure 29 14 Reset Input Timing tIL tIH VIH IRQ0 to IRQ5 NMI IC ADTRG TMBI FTIA FTIB FTIC FTID TRIG VIL Figure 29 15 Input Timing...

Page 879: ...n 4 SCK1 Clock synchronization 6 Input clock cycle tscyc SCK2 2 tcyc Input clock pulse width tSCKW SCK1 SCK2 0 4 0 6 tscyc SCK1 1 5 tcyc Input clock rise time tSCKr SCK2 60 ns SCK1 1 5 tcyc Input cloc...

Page 880: ...VIL or VOL VIH or VOH SCK1 tSCKW tscyc Figure 29 16 SCK1 Clock Timing VIL VIH tTXD SCK1 SCK2 SO1 SO2 SI1 SI2 tRXS tRXH Figure 29 17 SCI I O Timing Clock Synchronization Mode VIH VIH VIL CS SCK2 tCSH...

Page 881: ...Rev 2 0 11 00 page 854 of 1037 LSI output pin Timing reference level VOH 2 0 V VOL 0 8 V 30 pF 12k 2 4k Vcc Figure 29 19 Output Load Conditions...

Page 882: ...tcyc SCL input low pulse width tSCLL 5 tcyc SCL SDA input rise time tsr 7 5 tcyc SCL SDA input fall time tsf 300 ns SCL SDA input spike pulse removal time tsp 1 tcyc SDA input bus free time tBUF 5 tc...

Page 883: ...H tSr tSDAH tSCL tSCLL tSCLH tSf tSTAS tSP tSTOS tSDAS VIL VIH SDA SCL P S Sr P S P and Sr denote the following S Start conditions P Stop conditions Sr Re transmit start conditions Note tBUF Figure 29...

Page 884: ...ns Test Conditions Min Typ Max Unit Note Analog power supply voltage AVcc AVcc Vcc 0 3 Vcc Vcc 0 3 V Analog input voltage AVIN AN0 to AN7 AN8 to ANB AVss AVcc V AICC AVcc AVcc 5 0V 2 0 mA Analog power...

Page 885: ...4 0 46 0 CTLGR3 0 CTLGR2 1 CTLGR1 0 CTLGR0 1 f 10kHz 44 5 46 5 48 5 CTLGR3 0 CTLGR2 1 CTLGR1 1 CTLGR0 0 f 10kHz 47 0 49 0 51 0 CTLGR3 0 CTLGR2 1 CTLGR1 1 CTLGR0 1 f 10kHz 49 5 51 5 53 5 CTLGR3 1 CTLGR...

Page 886: ...Rise threshold level 2 25 CFG input threshold value V THCF CFG Fall threshold level 2 75 V V THDF Rising edge Schmidt level 1 95 DFG Schmidt input V THDF DFG Falling edge Schmidt level 1 85 V V THDP...

Page 887: ...nless otherwise specified Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Note Digital input high voltage VIH 0 8 Vcc Vcc 0 3 Digital input low voltage VIL COMP EXCTL EXCAP EXTTRG...

Page 888: ...register 2 EAd Destination operand EAs Source operand EXR Extend register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Pr...

Page 889: ...16 bit R0 to R7 or 32 bit ER0 to ER7 2 MAC register cannot be used in this LSI Condition Code Notation Symbol Description Modified according to the instruction result Not fixed value not guaranteed 0...

Page 890: ...4 4 2 4 6 2 4 6 4 6 4 6 6 8 6 8 MOV POP PUSH LDM STM MOVFPE MOVTPE Mnemonic Size Addressing Mode and Instruction Length Bytes xx Rn ERn d ERn ERn ERn aa d PC aa xx 8 Rd8 Rs8 Rd8 ERs Rd8 d 16 ERs Rd8 d...

Page 891: ...Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 C Rd8 Rd8 Rs8 C Rd8 ERd32 1 ERd32 ERd32 2 ERd32 ERd32 4 ERd32 Rd8 1 Rd8 Rd16 1 Rd16 Rd16 2 Rd16 ERd32 1 ERd32 ERd32 2 ERd32 Rd8 10 Deci...

Page 892: ...2 4 2 2 4 2 2 4 2 2 2 AND OR XOR NOT Mnemonic Size xx Rn ERn d ERn ERn ERn aa d PC aa Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 R...

Page 893: ...B Rd ROTR B 2 Rd ROTR W Rd ROTR W 2 Rd ROTR L ERd ROTR L 2 ERd B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2...

Page 894: ...6 8 4 6 8 BSET BCLR BNOT BTST BLD BILD BST BIST BAND Mnemonic Size xx Rn ERn d ERn ERn ERn aa d PC aa xx 3 of Rd8 1 xx 3 of ERd 1 xx 3 of aa 8 1 xx 3 of aa 16 1 xx 3 of aa 32 1 Rn8 of Rd8 1 Rn8 of ER...

Page 895: ...ic Size xx Rn ERn d ERn ERn ERn aa d PC aa C xx 3 of Rd8 C C xx 3 of ERd C C xx 3 of aa 8 C C xx 3 of aa 16 C C xx 3 of aa 32 C C xx 3 of Rd8 C C xx 3 of ERd C C xx 3 of aa 8 C C xx 3 of aa 16 C C xx...

Page 896: ...on H N Z V C Advanced Mode 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 Always Never C Z 0 C Z 1 C 0 C 1 Z 0 Z 1 V 0 V 1 N 0 N 1 N V 0 N V 1 if condition is true then PC PC d else next 2 3...

Page 897: ...TC ANDC ORC XORC NOP Mnemonic Size xx Rn ERn d ERn ERn ERn aa d PC aa PC SP CCR SP EXR SP Vector PC EXR SP CCR SP PC SP Transition to power down state xx 8 CCR xx 8 EXR Rs8 CCR Rs8 EXR ERs CCR ERs EXR...

Page 898: ...l setting value of R4L or R4 3 Only register ER0 ER1 ER4 or ER5 should be used when using the TAS instruction 1 7 states when the number of return retract registers is 2 9 states when the number of re...

Page 899: ...BNE d 16 BEQ d 8 BEQ d 16 BVC d 8 BVC d 16 BVS d 8 BVS d 16 Mnemonic Instruction Format 1st byte B B W W L L L L L B B B B W W L L B B B B B B B 8 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4...

Page 900: ...B B B B B B B B B B B B B B 4 5 4 5 4 5 4 5 4 5 4 5 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A 8 B 8 C 8 D 8 E 8 F 8 2 D F A A 2 D F A A 6 C E A A 7 C E A A 4 C E A A 7 D F A A A B...

Page 901: ...B B B B B B B 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 5 C E A A 7 C E A A 1 D F A A 1 D F A A 4 C E A A 0 D F A A 0 D F A A 5 C 7 D F A A 1 IMM 0 erd abs 1...

Page 902: ...tion Format 1st byte Cannot be used in this LSI B B B B B B B B B B B B B B B B B W W L L B B B W W L L B W B W W L W L 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 1 1 1 1 3 C...

Page 903: ...ion Format Cannot be used in this LSI 1st byte B W W L L B B B B W W W W W W W W W W W W L L L L L B B B B B B B B B B B B 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 6 6 7 6 2 6 6...

Page 904: ...Cannot be used in this LSI B B B B W W W W W W W W W W W W W W W L L L L L L L L L L L L L B B B W B W B W L 6 3 6 6 7 0 6 6 7 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 1 1 1 0 C rs A A 9...

Page 905: ...2 Rd ROTXR L ERd ROTXR L 2 ERd RTE RTS Mnemonic Instruction Format 1st byte B W L B B W W L L B B W L W L B B W W L L B B W W L L B B W W L L B B W W L L 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 1 1...

Page 906: ...ERd Mnemonic Instruction Format 1st byte B B W W L L B B W W L L B B W W L L B B W W L L B B W W W W W W W W W W W W L L L L L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 907: ...W L L L L L B B B B B W W L L B B 1 7 1 7 1 1 1 1 B 1 0 5 D 1 7 6 7 0 0 0 8 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 5 1 rs 3 rs 3 1 ers 0 8 9 IMM rs E IMM IMM rs 5 rs 5 F IMM 4 rd rd rd 0 erd 0 erd 0 erd...

Page 908: ...address register or 32 bit register is selected in 3 bits ers erd ern and erm correspond to the operand type ERs ERd ERn and Rm respectively The following table shows the correspondence between the r...

Page 909: ...RC OR BCC RTS OR BOR BIOR 6 ANDC AND BNE RTE AND 5 XORC XOR BCS BSR XOR BXOR BIXOR BAND BIAND 7 LDC BEQ TRAPA BST BIST BLD BILD 8 BVC MOV 9 BVS A BPL JMP B BMI EEPMOV C BGE BSR D BLT MOV E ADDX SUBX B...

Page 910: ...LL SHLR ROTXL ROTXR BCC MOVFPE OR OR 5 INC EXTU DEC BCS XOR XOR 6 MAC BNE AND AND 7 INC SHLL SHLR ROTXL ROTXR EXTU DEC BEQ LDC STC 8 SLEEP BVC MOV ADDS SHAL SHAR ROTL ROTR NEG SUBS 9 BVS A CLRMAC BPL...

Page 911: ...ighest bit is set to 1 Notes AH AL BH BL CH CL 01C05 01D05 01F06 7Cr06 1 7Cr07 1 7Dr06 1 7Dr07 1 7Eaa6 2 7Eaa7 2 7Faa6 2 7Faa7 2 0 MULXS BSET BSET BSET BSET 1 DIVXS BNOT BNOT BNOT BNOT 2 MULXS BCLR BC...

Page 912: ...0 HH highest bit is set to 1 Note Absolute address is set at aa 5th byte 6th byte EH EL FH FL 7th byte 8th byte GH GL HH HL 6A10aaaa6 6A10aaaa7 6A18aaaa6 6A18aaaa7 AHALBHBLCHCLDHDLEH EL 0 BSET 1 BNOT...

Page 913: ...ber of execution states can be obtained from the equation below Number of execution states I SI J SJ K SK L SL M SM N SN 1 Examples of execution state number calculation The conditions are as follows...

Page 914: ...or Each Execution Status Cycle Target of Access On Chip Supporting Module Execution Status Cycle On Chip Memory 8 bit bus 16 bit bus Instruction fetch SI Branch address read SJ Stack operation SK Byte...

Page 915: ...W xx 16 Rd AND W Rs Rd AND L xx 32 ERd AND L ERs ERd 1 1 2 1 3 2 ANDC ANDC xx 8 CCR ANDC xx 8 EXR 1 2 BAND BAND xx 3 Rd BAND xx 3 ERd BAND xx 3 aa 8 BAND xx 3 aa 16 BAND xx 3 aa 32 1 2 2 3 4 1 1 1 1...

Page 916: ...1 2 2 3 4 1 1 1 1 BILD BILD xx 3 Rd BILD xx 3 ERd BILD xx 3 aa 8 BILD xx 3 aa 16 BILD xx 3 aa 32 1 2 2 3 4 1 1 1 1 BIOR BIOR xx 8 Rd BIOR xx 8 ERd BIOR xx 8 aa 8 BIOR xx 8 aa 16 BIOR xx 8 aa 32 1 2 2...

Page 917: ...BSET Rn aa 32 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 BSR BSR d 8 2 2 BSR d 16 2 2 1 BST BST xx 3 Rd BST xx 3 ERd BST xx 3 aa 8 BST xx 3 aa 16 BST xx 3 aa 32 1 2 2 3 4 2 2 2 2 BTST BTST xx 3 Rd BTST xx 3...

Page 918: ...EXTU L ERd 1 1 INC INC B Rd INC W 1 2 Rd INC L 1 2 ERd 1 1 1 JMP JMP ERN JMP aa 24 2 2 1 JMP aa 8 2 2 1 JSR JSR ERn 2 2 JSR aa 24 2 2 1 JSR aa 8 2 2 2 LCD LDC xx 8 CCR LDC xx 8 EXR LDC Rs CCR LDC Rs...

Page 919: ...ERs Rd MOV W aa 16 Rd MOV W aa 32 Rd MOV W Rs ERd MOV W Rs d 16 ERd MOV W Rs d 32 ERd MOV W Rs ERd MOV W Rs aa 16 MOV W Rs aa 32 MOV L xx 32 ERd MOV L ERs ERd MOV L ERs ERd MOV L d 16 ERs ERd MOV L d...

Page 920: ...Rd OR L ERs ERd 1 1 2 1 3 2 ORC ORC xx 8 CCR ORC xx 8 EXR 1 2 POP POP W Rn POP L ERn 1 2 1 2 1 1 PUSH PUSH W Rn PUSH L ERn 1 2 1 2 1 1 ROTL ROTL B Rd ROTL B 2 Rd ROTL W Rd ROTL W 2 Rd ROTL L ERd ROTL...

Page 921: ...LR SHLR B Rd SHLR B 2 Rd SHLR W Rd SHLR W 2 Rd SHLR L ERd SHLR L 2 ERd 1 1 1 1 1 1 SLEEP SLEEP 1 1 STC STC B CCR Rd STC B EXR Rd STC W CCR ERd STC W EXR ERd STC W CCR d 16 ERd STC W EXR d 16 ERd STC W...

Page 922: ...d SUBX Rs Rd 1 1 TAS TAS ERd 3 2 2 TRAPA TRAPA x 2 2 2 2 3 1 2 XOR XOR B xx 8 Rd XOR B Rs Rd XOR W xx 16 Rd XOR W Rs Rd XOR L xx 32 ERd XOR L ERs ERd 1 1 2 1 3 2 XORC XORC xx 8 CCR XORC xx 8 EXR 1 2 N...

Page 923: ...n Order of execution Effective address is read by word Read write not executed The 2nd word of the instruction currently being executed is read by word Legend R B Read by byte R W Read by word W B Wri...

Page 924: ...A BLS d 8 R W NEXT R W EA BCC d 8 BHS d 8 R W NEXT R W EA BCS d 8 BLO d 8 R W NEXT R W EA BNE d 8 R W NEXT R W EA BEQ d 8 R W NEXT R W EA BVC d 8 R W NEXT R W EA BVS d 8 R W NEXT R W EA BPL d 8 R W NE...

Page 925: ...R W 2nd R W 3rd R W 4th R B EA R W M NEXT BIOR xx 3 Rd R W NEXT BIOR xx 3 ERd R W 2nd R B EA R W M NEXT BOIR xx 3 aa 8 R W 2nd R B EA R W M NEXT BOIR xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BOIR...

Page 926: ...on 1 state R W EA W W M stack H W W stack L BST xx 3 Rd R W NEXT BST xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BST xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BST xx 3 aa 16 R W 2nd R W 3rd R B M E...

Page 927: ...aa 8 R W aa 8 W W M stack H W W stack L R W EA LCD xx 8 CCR R W NEXT LCD xx 8 EXR R W 2nd R W NEXT LCD Rs CCR R W NEXT LCD Rs EXR R W NEXT LCD ERs CCR R W 2nd R W NEXT R W EA LCD ERs EXR R W 2nd R W...

Page 928: ...ration 1 state R W EA MOV W aa 16 Rd R W 2nd R W NEXT R W EA MOV W aa 32 Rd R W 2nd R W 3rd R W NEXT R B EA MOV W Rs ERd R W NEXT W W EA MOV W Rs d 16 ERd R W 2nd R W NEXT W W EA MOV W Rs d 32 ERd R W...

Page 929: ...W NEXT OR W Rs Rd R W NEXT OR L xx 32 ERd R W 2nd R W 3rd R W NEXT OR L ERs ERd R W 2nd R W NEXT ORC xx 8 CCR R W NEXT ORC xx 8 EXR R W 2nd R W NEXT POP W Rn R W NEXT Internal operation 1 state R W EA...

Page 930: ...rnal operation M STC CCR Rd R W NEXT STC EXR Rd R W NEXT STC CCR ERd R W 2nd R W NEXT W W EA STC EXR ERd R W 2nd R W NEXT W W EA STC CCR d 16 ERd R W 2nd R W 3rd R W NEXT W W EA STC EXR d 16 ERd R W 2...

Page 931: ...W NEXT Reset exception handling R W M VEC R W VEC 2 Internal operation 1 state R W 5 Interrupt exception handling R W 6 Internal operation 1 state W W stack L W W stack H W W stack EXR R W M VEC R W...

Page 932: ...e following tables is as follows m 31 Longword size m 15 Word size m 7 Byte size Si Bit i of source operand Di Bit i of destination operand Ri Bit i of result Dn Specified bit of destination operand N...

Page 933: ...P Sm 5P ADDS ADDX H Sm 4 Dm 4 Dm 4 5P Sm 4 5P N Rm Z Z 5P 5 V Sm Dm 5P 6P P Rm C Sm Dm Dm 5P Sm 5P AND 0 N Rm Z 5P 5P 5 ANDC Value in the bit corresponding to execution result is stored No flag change...

Page 934: ...l addition carry DAS N Rm Z 5P 5P 5 C Decimal subtraction borrow DEC N Rm Z 5P 5P 5 V Dm 5P DIVXS N Sm P 6P Dm Z 6P 6P 6 DIVXU N Sm Z 6P 6P 6 EEPMOV EXTS 0 N Rm Z 5P 5P 5 EXTU 0 0 Z 5P 5P 5 INC N Rm Z...

Page 935: ...responding to execution result is stored No flag change when EXR POP 0 N Rm Z 5P 5P 5 PUSH 0 N Rm Z 5P 5P 5 ROTL 0 N Rm Z 5P 5P 5 C Dm In case of 1 bit C Dm 1 In case of 2 bits ROTR 0 N Rm Z 5P 5P 5 C...

Page 936: ...m Z 5P 5P 5 C Dm In case of 1 bit C Dm 1 In case of 2 bits SHLR 0 0 N Rm Z 5P 5P 5 C D0 In case of 1 bit C D1 In case of 2 bits SLEEP STC STM STMAC Cannot be used in this LSI SUB H Sm 4 P P Rm 4 Sm 4...

Page 937: ...GKp5 CGKp4 CGKp3 CGKp2 CGKp1 CGKp0 H D012 CGKs15 CGKs14 CGKs13 CGKs12 CGKs11 CGKs10 CGKs9 CGKs8 H D013 CGKs W 16 16 CGKs7 CGKs6 CGKs5 CGKs4 CGKs3 CGKs2 CGKs1 CGKs0 H D014 CAp15 CAp14 CAp13 CAp12 CAp11...

Page 938: ...CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8 H D057 CFRLDR W 16 16 CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0 H D058 CFVCR R W 8 16 CFCS1 CFCS0 CFOVF CFRFON CF R UNR CPCNT CFRCS1 CFRCS0 H D0...

Page 939: ...4 CMT43 CMT42 CMT41 CMT40 H D08A CMT5B CMT5A CMT59 CMT58 H D08B RCDR5 W 16 16 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 H D08C DI O R W 8 VCTR2 VCTR1 VCTR0 BPON BPS BPF DI O H D08D BTPR R W 8 16...

Page 940: ...RHSW2 IRRHSW1 H D0BB SIRQR2 R W 8 16 IRRSNC IRRCTL Servo interrupt control H D0C0 R W 8 8 H D0C1 R W 8 8 H D0C2 R W 8 8 H D0C3 R W 8 8 H D0C4 R W 8 8 H D0C5 R W 8 8 H D0C6 R W 8 8 H D0C7 R W 8 8 H D0C...

Page 941: ...ICRDL0 Timer X1 OCRA and OCRB addresses are the same Switched by OCSR bit in IOCR H D110 TMB R W 8 8 TMB17 TMBIF TMPIE TMP12 TMP11 TCB10 H D111 TCB R 8 8 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB1...

Page 942: ...KS0 BC2 BC1 BC0 H D15F SAR R W 8 8 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS IIC interface Access varies depending on ICE bit H FFB0 TA023 TA022 TA021 TA020 TA019 TA018 TA017 TA016 H FFB1 TA015 TA014 TA01...

Page 943: ...RTPEGR0 H FFE5 RTPSR R W 8 8 RTPSR7 RTPSR6 RTPSR5 RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0 RTP TRG select H FFE8 SYSCR R W 8 8 INTM1 INTM0 XRST NMIEG1 NMIEG0 H FFE9 MDCR R W 8 8 MDS0 H FFEA SBYCR R W 8 8 SS...

Page 944: ...4 7 W 6 W 9 W 8 W 11 W 10 W W W W W W W W 12 H D004 Coefficient DAp Drum Digital Filter H D005 Coefficient DAp Drum Digital Filter H D006 Coefficient DBp Drum Digital Filter H D007 Coefficient DBp Dru...

Page 945: ...ter Bit Initial value R W W 13 W 14 W 15 1 0 3 2 5 4 7 W 6 W 9 W 8 W 11 W 10 W W W W W W W W 12 H D010 Gain Constant CGKp Capstan Digital Filter H D011 Gain Constant CGKp Capstan Digital Filter H D012...

Page 946: ...ient CAs Capstan Digital Filter H D01A Coefficient CBs Capstan Digital Filter H D01B Coefficient CBs Capstan Digital Filter Bit Initial value R W W 13 W 14 W 15 1 0 3 2 5 4 7 W 6 W 9 W 8 W 11 W 10 W W...

Page 947: ...r H D023 Delay Initialization Register DZp Digital filter H D024 Delay Initialization Register CZs Digital filter H D025 Delay Initialization Register CZs Digital filter H D026 Delay Initialization Re...

Page 948: ...system filter computation start bit 0 Phase system filter computation is OFF Phase system computation result Y is not added to Es 1 Phase system filter computation is ON Drum phase system Z 1 initial...

Page 949: ...filter computation start bit 0 Phase system filter computation is OFF Phase system computation result Y is not added to Es 1 Phase system filter computation is ON Capstan phase system Z 1 initializat...

Page 950: ...ch 1 Transfer data at the time of error data write Capstan speed system error data transfer bit 0 Transfer data by DVCFG signal latch 1 Transfer data at the time of error data write Drum speed system...

Page 951: ...W 14 0 W 15 1 0 3 2 5 4 7 1 W 6 1 W 9 1 W 8 1 W 11 1 W 10 1 W 1 W W W W W W W 12 1 1 1 1 1 1 Bit Initial value R W H D036 DFG Lock Lower Data Register DFRLDR Drum Error Detector H D037 DFG Lock Lower...

Page 952: ...Limit function OFF 1 Limit function ON Drum lock flag 0 Drum speed system is not locked 1 Drum speed system is locked Drum phase system filter computation auto start bit 0 Filter computation by drum l...

Page 953: ...ng edge 1 Latch at falling edge Bit Initial value R W Clock source select bit DPCS1 DPCS0 0 0 s 1 s 2 1 0 s 3 1 s 4 Counter overflow flag 0 Normal status 1 Counter overflows Description H D03A Specifi...

Page 954: ...4 7 0 W 6 0 W 9 0 W 8 0 W 11 0 W 10 0 W 0 W W W W W W W 12 0 0 0 0 0 0 Bit Initial value R W H D052 CFG Speed Error Data Register CFER Capstan Error Detector 0 R W 13 0 R W 14 0 R W 15 1 0 3 2 5 4 7...

Page 955: ...at the time of drum lock detection Bit Initial value R W Capstan lock counter setting bit CFRCS1 CFRCS0 Description 0 0 Underflow by 1 lock detection 1 Underflow by 2 lock detections 1 0 Underflow by...

Page 956: ...DVCTL signal 1 Preset by REF30P signal and latch by DVCFG2 signal Bit Initial value R W Clock source select bit CPCS1 CPCS0 0 0 s 1 s 2 1 0 s 4 1 s 8 Counter overflow flag 0 Normal status 1 Counter ov...

Page 957: ...it Initial value R W Note Note that only detected error data can be read H D05E Capstan Phase Error Data Register 2 CPER2 Capstan Error Detector 0 R W 13 0 R W 14 0 R W 15 1 0 3 2 5 4 7 0 R W 6 0 R W...

Page 958: ...FIFO1 is full FIFO2 empty flag 0 Data remains in FIFO2 1 FIFO2 is empty FIFO1 empty flag 0 Data remains in FIFO1 1 FIFO1 is empty FIFO2 overwrite flag 0 Normal operation 1 Data is written to FIFO1 wh...

Page 959: ...nce register 2 is disabled Mode select bit 0 Signal mode 1 Loop mode DFG edge select bit 0 Calculated by DFG rising edge 1 Calculated by DFG falling edge Interrupt select bit 0 Interrupt request is ge...

Page 960: ...Output stage 0 to 6 of FIFO1 1 Output stage 0 to 7 of FIFO1 1 0 0 0 Output stage 0 to 8 of FIFO1 1 Output stage 0 to 9 of FIFO1 1 0 Setting disabled 1 1 0 0 1 1 0 1 Note Don t care FIFO2 stage setting...

Page 961: ...9 8 W FTPRA8 11 W FTPRA11 10 W FTPRA10 FTPRA13 FTPRA12 FTPRA15 FTPRA14 12 13 14 15 W W W W H D066 FIFO Timer Capture Register 1 FTCTR HSW Timing Generator Bit Initial value R W 1 0 R FTCTR1 0 0 R FTCT...

Page 962: ...0 W ISEL2 W W W CCLR CKSL Interrupt select bit 0 Interrupt request is generated by clear signal of 16 bit timer counter 1 Interrupt request is generated by VD signal in PB mode DFG counter clear bit...

Page 963: ...tput 1 Narrow FF signal output COMP polarity select bit 0 Positive 1 Negative C Rotary synchronization control bit 0 Synchronous 1 Asynchronous H AmpSW synchronization control bit 0 Synchronous 1 Asyn...

Page 964: ...l 1 0 Negative polarity Figure 28 46 1 Positive polarity Figure 28 45 1 0 Immediate level high impedance when HiZ bit 1 1 High level Bit Initial value R W H D070 X Value Data Register XDR X Value TRK...

Page 965: ...s generated only by XDR setting value 1 CAPREF30 is generated by XDR and TRDR setting values Reference signal select bit 0 Generated by REF30P signal 1 Generated by external referece signal Clock sour...

Page 966: ...data select bit Note When PWMs output data from the digital filter circuit the data consisting of the speed and phase filtering results are modulated by PWMs and output from the CAPPWM and DRMPWM pins...

Page 967: ...W FSLB W FSLC 0 W NT PL FSLA CCS LCTL UNCTL SLWM NTSC PAL select bit 0 NTSC mode frame rate 30 Hz 1 PAL mode frame rate 25 Hz Long CTL bit 0 Clock source CCS operates at the setting value 1 Clock sou...

Page 968: ...5 1 0 3 2 5 4 7 6 9 8 11 10 CMT11 W 12 0 CMT10 W 0 CMT13 W 0 CMT12 W 0 CMT15 W 0 CMT14 W 0 CMT17 W 0 CMT16 W 0 CMT19 W 0 CMT18 W 0 CMT1B W 0 CMT1A W 0 Bit Initial value R W H D084 REC CTL Duty Data Re...

Page 969: ...CMT5B W 0 CMT5A W 0 Bit Initial value R W H D08C Duty I O Register DI O CTL Circuit 0 1 1 0 R W 2 0 W 3 0 4 5 1 6 7 R W W W VCTR0 1 W VCTR1 1 W VCTR2 BPON BPS BPF DI O 1 Note Only 0 can be written Bit...

Page 970: ...4 1 REF4 W 3 1 REF3 W 2 1 REF2 W 1 1 REF1 W 0 1 REF0 W Bit Initial value R W H D092 Reference Frequency Register 2 CRF Reference Signal Generator 15 1 CRF15 W 14 1 CRF14 W 13 1 CRF13 W 12 1 CRF12 W 11...

Page 971: ...signal rising ODD VideoFF counter set 0 VideoFF signal turns counter set OFF 1 VideoFF signal turns counter set OFF VideoFF edge select bit 0 Set at VideoFF signal rising 1 Set at VideoFF signal fall...

Page 972: ...External sync signal edge select bit 0 Rising edge 1 Falling edge CFG flag 0 CFG level is low 1 CFG level is high HSW flag 0 HSW level is low 1 HSW level is high CTL flag 0 REC or PB CTL level is low...

Page 973: ...it 0 PB ASM to REC transition timing sync ON 1 PB ASM to REC transition timing sync OFF CFG frequency division edge select bit 0 Execute frequency division operation at CFG rising edge 1 Execute frequ...

Page 974: ...gnal input 1 Digital signal input method for CFG signal input CTLSTOP bit 0 CTL circuit operates 1 CTL circuit does not operate EXCTL pin function switch bit 0 EXCTL PS4 pin functions as EXCEL input p...

Page 975: ...on 0 0 0 REF30 signal is output from SV2 output pin 1 CAPREF30 signal is output from SV2 output pin 1 0 CREF signal is output from SV2 output pin 1 CTLMONI signal is output from SV2 output pin 1 0 0 D...

Page 976: ...0 44 0 dB 1 46 5 dB 1 0 49 0 dB 1 51 5 dB 1 0 0 0 54 0 dB 1 56 5 dB 1 0 59 0 dB 1 61 5 dB 1 0 0 64 0 dB 1 66 5 dB 1 0 69 0 dB 1 71 5 dB Bit Initial value R W Note With a setting of 64 0dB or more the...

Page 977: ...TR0 0 W HRTR7 W W W HRTR6 HRTR5 Bit Initial value R W H D0B3 H Pulse Width Setting Register HPWR Sync Detector Servo 0 0 1 0 W 2 0 W 3 0 4 5 6 1 7 W W HPWR3 HPWR2 HPWR1 HPWR0 1 1 1 Bit Initial value R...

Page 978: ...Only 0 can be written Interrupt select bit 0 Noise level interrupt 1 VD interrupt Noise detection flag 0 Noise count is less than four times of NDR setting value 1 Noise count is over four times of N...

Page 979: ...RM1 1 Interrupt request is enabled by IRRDRM1 Capstan phase error detection interrupt enable bit 0 Interrupt request is disabled by IRRCAP3 1 Interrupt request is enabled by IRRCAP3 Capstan speed erro...

Page 980: ...ECTL 1 1 1 1 1 Vertical sync signal interrupt enable bit 0 Interrupt vertical sync signal interrupt request is disabled by IRRSNC 1 Interrupt vertical sync signal interrupt request is enabled by IRRSN...

Page 981: ...or detector OVF latch interrupt request bit 0 Capstan phase error detector OVF latch interrupt request is not generated 1 Capstan phase error detector OVF latch interrupt request is generated Capstan...

Page 982: ...ated 1 Sync signal detector VD noise interrupt request is generated CTL interrupt request bit 0 CTL interrupt request is not generated 1 CTL interrupt request is generated Bit Initial value R W H D0E0...

Page 983: ...e bit 0 Transfer end interrupt request is disabled 1 Transfer end interrupt request is enabled Transfer interrupt enable bit 0 Transfer interrupt request is disabled 1 Transfer interrupt request is en...

Page 984: ...hen 0 is written after reading 1 1 Setting conditions When extra pulse is over applied to correct transfer clock or clock input is generated after transfer end when using external clock Wait flag 0 Cl...

Page 985: ...errupt request ICIB is enabled 0 1 Input capture B interrupt enable bit ICFC interrupt request ICIC is disabled ICFC interrupt request ICIC is enabled 0 1 Input capture C interrupt enable bit ICFD int...

Page 986: ...conditions When FRC changes from H FFFF to H 0000 0 1 Input capture flag D Clearing conditions When 0 is written to ICFD after reading ICFD 1 Setting conditions When input capture signal is generated...

Page 987: ...0 R W 6 0 8 0 R W 10 0 12 0 14 FRC FRCH FRCL R W R W R W R W 0 R W 0 Bit Initial value R W H D104 Output Compare Register AH BH OCRAH OCRBH Timer X1 H D105 Output Compare Register AL BL OCRAL OCRBL T...

Page 988: ...f input capture input C Capture at rising edge of input capture input C 0 1 Input capture edge select C Capture at falling edge of input capture input D Capture at rising edge of input capture input D...

Page 989: ...selected for input capture C input DVCTL is selected for input capture C input 0 1 Input capture input select C FTID pin is selected for input capture D input NHSW is selected for input capture D inp...

Page 990: ...r BL ICRBL Timer X1 H D10C Input Capture Register CH ICRCH Timer X1 H D10D Input Capture Register CL ICRCL Timer X1 H D10E Input Capture Register DH ICRDH Timer X1 H D10F Input Capture Register DL ICR...

Page 991: ...request is enabled 0 1 Timer B interrupt enable bit 0 0 0 Internal clock Count at 16384 TMB11 TMB10 TMB12 Clock select 0 1 Internal clock Count at 4096 1 0 0 0 0 Internal clock Count at 1024 1 1 Inter...

Page 992: ...terrupt request flag Clearing conditions When 0 is written after reading 1 Setting conditions When LTC overflow underflow or compare match clear occurs 0 1 Timer L interrupt enable bit Timer L interru...

Page 993: ...0 0 1 0 R 2 0 3 0 4 5 6 0 7 R R R R LTC6 0 R LTC5 0 R LTC4 0 R LTC7 LTC3 LTC2 LTC1 LTC0 Bit Initial value R W H D113 Reload Compare Match Register RCR Timer L 0 0 1 0 W 2 0 3 0 4 5 6 0 7 W W W W RCR6...

Page 994: ...ot used as reload timer TMRU 2 is used as reload timer 0 1 Execution non execution of reload by TMRU 2 Reload at CFG rising edge Reload at TMRU underflow 0 1 TMRU 2 reload timing select bit 0 0 Count...

Page 995: ...ount at 1024 Interrupt select bit Interrupt request by TMRU 2 capture signal is enabled Interrupt request by slow tracking mono multi end is enabled 0 1 Capture signal flag Clearing conditions When 0...

Page 996: ...RC22 R TMRC21 R TMRC20 Bit Initial value R W H D11C Timer R Load Register 1 TMRL1 Timer R 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 W TMR17 W TMR16 W TMR15 W TMR14 W TMR13 W TMR12 W TMR11 W TMR10 Bit Initial va...

Page 997: ...bit TMRI1 interrupt request is disabled TMRI1 interrupt request is enabled 0 1 TMRI1 interrupt enable bit TMRI1 interrupt request flag Clearing conditions When 0 is written after reading 1 Setting co...

Page 998: ...1 7 R W PWCR0 1 Clock select bit Note t PWM input clock frequency Input clock is 2 t 2 Generate PWM waveform with conversion frequency of 16384 and minimum pulse width of 1 Input clock is 4 t 4 Gener...

Page 999: ...W 0 W 5 6 0 7 PW34 PW33 PW32 PW31 PW30 0 W PW37 W W W PW36 PW35 Bit Initial value R W H D12A 8 Bit PWM Control Register PW8CR 8 Bit PWM 0 0 1 0 R W 2 0 R W 3 0 4 5 6 7 PWC3 PWC2 PWC1 PWC0 R W R W 1 1...

Page 1000: ...bits Frequency division clodk output select 0 0 0 PSS output 32 DCS1 DCS0 DCS2 1 PSS output 16 1 0 PSS output 8 1 PSS output 4 0 1 0 PSW output W 32 1 PSW output W 16 1 0 PSW output W 8 1 PSW output...

Page 1001: ...0 R 0 R 0 R 0 R ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 R 12 13 14 15 0 0 0 0 0 0 Bit Initial value R W H D132 Hardware Trigger A D Result Register H AHRH A D Converter H D133 Hardware Tri...

Page 1002: ...l 0 0 AN8 1 AN9 1 0 ANA 1 ANB Software channel select bits SCH3 SCH2 SCH1 SCH0 Analog input channel 0 0 0 0 AN0 1 AN1 1 0 AN2 1 AN3 1 0 0 AN4 1 AN5 1 0 AN6 1 AN7 1 0 0 0 AN8 1 AN9 1 0 ANA 1 ANB 1 Soft...

Page 1003: ...conversion was canceled by the start of hardware triggered A D conversion Software triggered A D conversion cancel flag 0 No contention for A D conversion 1 Indicates that software triggered A D conve...

Page 1004: ...xternal triggered ADTRG A D conversion is selected Bit Initial value R W H D138 Timer Load Register K TLK Timer J 0 1 1 1 W 2 1 W 3 1 4 1 W 5 1 6 1 7 W W W TLR25 W TLR26 1 W TLR27 TLR24 TLR23 TLR22 TL...

Page 1005: ...selection is set in edge select register IEGR See section explaining edge select register IEGR When using external clock in remote control mode set opposite edges for IRQ1 and IRQ2 edges eg When fall...

Page 1006: ...abled TMJ2I interrupt request is enabled 0 1 TMJ2I interrupt enable bit TMJ1I interrupt request is disabled TMJ1I interrupt request is enabled 0 1 TMJ1I interrupt enable bit PB or REC CTL MON0 MON1 DV...

Page 1007: ...1 Note Only 0 can be written to clear the flag TMJ1I interrupt request flag Clearing conditions When 0 is written after reading 1 Setting conditions When TMJ 1 underflows 0 1 TMJ2I interrupt request f...

Page 1008: ...eption a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 2 When odd parity is set parity bit addition is performed in transmission so that...

Page 1009: ...Rev 2 0 11 00 page 982 of 1037 H D149 Bit Rate Register BRR1 SCI1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W...

Page 1010: ...the MPIE bit is cleared to 0 2 When data with MPB 1 is received Multiprocessor interrupt are enabled Receive interrupt RXI requests receive error interrupt ERI requests and setting of the RDRF FER and...

Page 1011: ...Rev 2 0 11 00 page 984 of 1037 H D14B Transmit Data Register TDR1 SCI1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W...

Page 1012: ...continued either Receive data register full Clearing conditions When 0 is written in RDRF after reading RDRF 1 Setting conditions When serial reception ends normally adn receive data is transferred f...

Page 1013: ...0 1 Serial communication inteface mode select Data invert TDR1 contents are transmitted without modification Receive data is stored in RDR1 without modification TDR1 contents are onverted before bein...

Page 1014: ...when WAIT 1 3 At the end of data transfer at the rise of the 9th transmit clock pulse and at the fall of the 8th transmit receive clock pulse when a wait is inserted 4 When a slave address is received...

Page 1015: ...in AASX after reading AASX 1 2 When a start condition is detected 3 In master mode 1 Second slave address recognized Setting conditions When the second slave address is detected in slave receive mode...

Page 1016: ...W 4 ICDR4 R W 3 ICDR3 R W 0 ICDR0 R W 2 ICDR2 R W 1 ICDR1 R W Bit Initial value R W H D15E Second Slave Address Register SARX IIC Bus Interface 7 SVAX6 0 R W 6 SVAX5 0 R W 5 SVAX4 0 R W 4 SVAX3 0 R W...

Page 1017: ...2 1 0 2 3 1 3 4 0 0 0 4 5 1 5 6 1 0 6 7 1 7 8 Bit Initial value R W Note See STCR Bit 6 IICX CKS2 CKS1 CKS0 Clock Transfer rate 5 MHz 8 MHz 10 MHz 0 0 0 0 28 179 kHz 286 kHz 357 kHz 1 40 125 kHz 200 k...

Page 1018: ...mat SAR slave address ignored SARX slave address recognized 1 I2 C bus format SAR and SARX slave addresses ignored Bit Initial value R W H FFB0 Trap Address Register 0 TAR0 ATC H FFB3 Trap Address Reg...

Page 1019: ...R W TRC2 TRC1 TRC0 1 Trap control 0 0 Address trap function 0 is disabled 1 Address trap function 0 is enabled Trap control 1 0 Address trap function 1 is disabled 1 Address trap function 1 is enable...

Page 1020: ...is disabled Interrupt request by Timer A TMAI is enabled 0 1 Timer A interrupt enable bit Timer A clock source is PSS Timer A clock source is PSW 0 1 Clock source prescaler select bit PSS 16384 TMA1 T...

Page 1021: ...WTCNT counts 0 1 NMI interrupt request is disabled Internal reset request is generated 0 1 Timer mode select bit Timer enable bit Reset or NMI Interval timer mode Sends the CPU an interval timer inter...

Page 1022: ...ata Register 1 PDR1 I O Port 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 0 7 0 R W R W R W R W 6 PDR14 PDR13 PDR12 PDR11 PDR10 PDR17 PDR16 PDR15 Bit Initial value R W H FFC2 Port Data Register 2 PDR2 I O...

Page 1023: ...lue R W H FFC6 Port Data Register 6 PDR6 I O Port 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 6 0 7 PDR64 PDR63 PDR62 PDR61 PDR60 0 R W PDR67 R W R W R W PDR66 PDR65 Bit Initial value R W H FFC7 Port Data...

Page 1024: ...H FFCE Port Mode Register 1 PMR1 I O Port 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 0 7 0 R W R W R W R W 6 PMR14 PMR13 PMR12 PMR11 PMR10 PMR17 PMR16 PMR15 P17 TMOW pin functions as P17 I O port P17 TMO...

Page 1025: ...as P3n I O port P3n PWMm pin functions as PWMm output port 0 1 P36 BUZZ pin functions as P36 I O port P36 BUZZ pin functions as BUZZ output port 0 1 P37 TMO pin functions as P37 I O port P37 TMO pin...

Page 1026: ...2 Port Control Register 2 PCR2 I O Port 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 0 7 0 W W W W 6 PCR24 PCR23 PCR22 PCR21 PCR20 PCR27 PCR26 PCR25 P2n pin functions as input port P2n pin functions as output port...

Page 1027: ...1 7 1 6 W PCR51 W PCR50 0 W PCR52 0 W PCR53 P5n pin functions as input port P5n pin functions as output port 0 1 n 3 to 0 Bit Initial value R W H FFD6 Port Control Register 6 PCR6 I O Port 0 0 1 0 W 2...

Page 1028: ...W H FFD8 Port Control Register 8 PCR8 I O Port 0 0 1 0 W 2 0 W 3 0 4 0 W 0 W 5 6 0 7 PCR84 PCR83 PCR82 PCR81 PCR80 0 W PCR87 W W W PCR86 PCR85 P8n pin functions as input port P8n pin functions as outp...

Page 1029: ...B event input edge select Bit Initial value R W H FFDD Port Mode Register 6 PMR6 I O Port 0 0 1 0 R W 2 0 R W 3 0 4 0 R W 0 R W 5 6 0 7 PMR64 PMR63 PMR62 PMR61 PMR60 0 R W PMR67 R W R W R W PMR66 PMR6...

Page 1030: ...nction select bit P81 EXCAP pin functions as P81 I O port P81 EXCAP pin functions as EXCAP input port 0 1 P81 EXCAP pin function select bit P80 EXTTRG pin functions as P80 I O port P80 EXTTRG pin func...

Page 1031: ...0 7 0 R W R W R W R W 6 PUR34 PUR33 PUR32 PUR31 PUR30 PUR37 PUR36 PUR35 P3n pin has no pull up MOS transistor P3n pin has pull up MOS transistor 0 1 n 7 to 0 Bit Initial value R W H FFE4 Realtime Out...

Page 1032: ...NMIEG0 0 0 0 0 Interrupt is controlled by I bit INTM0 INTM1 Interrupt control mode Interrupt control 1 1 Interrupt is controlled by I and UI bits and ICR 0 1 2 Cannot be used in the H8S 2194 Series 1...

Page 1033: ...Rev 2 0 11 00 page 1006 of 1037 H FFE9 Mode Control Register MDCR System Control 0 1 0 2 0 3 0 4 0 5 0 6 0 7 R MDS0 0 Note Determined by MD0 pin Mode select 0 Bit Initial value R W...

Page 1034: ...medium speed mode Transition to watch mode or high speed mode after execution of SLEEP instruction in subactive mode 0 1 Software standby System clock select System clock select 0 0 SCK0 SCK1 1 0 0 1...

Page 1035: ...dby mode When a SLEEP instruction is executed in subactive mode a transition is made directily to high speed mode or a transition is made to subsleep mode 0 1 Direct transfer on flag When a SLEEP inst...

Page 1036: ...TP1 R W 0 1 MSTP0 R W MSTPCRL Module stop Module stop mode is released Module stop mode is set 0 1 Bit Initial value R W H FFEE Serial Timer Control Register STCR System Control 7 0 6 IICX 0 R W 5 IIC...

Page 1037: ...sing edge of IRQ0 pin input 1 Interrupt request generaed at bath falling and rising edge of IRQ0 pin input Note Don t care IRQ5 to IRQ1 pins detected edge select bits Interrupt request generated at fa...

Page 1038: ...nput while rising edge detection is set IRQnEG 0 3 When a falling or rising edge occurs in IRQ0 input while both edge detection is set IRQ0EG1 1 0 1 n 5 to 0 Bit Initial value R W H FFF3 Interrupt Con...

Page 1039: ...low level is input to the FWE pin hardware protected state When a high level is input to the FWE pin 0 1 Erase verify Erase verify mode cleared Transition to erase verify mode Setting condition When...

Page 1040: ...t to the FWE pin 0 1 Erase verify Erase verify mode cleared Transition to erase verify mode Setting condition When FWE 1 and SWE 1 0 1 Erase setup bit 1 Erase setup cleared Erase setup Setting conditi...

Page 1041: ...ror protection is disabled Clearing condition Reset or hardware standby mode An error has occurred during flash memeory programming erasing Flash memory program erase protection error protection is en...

Page 1042: ...ee section 8 8 3 Error Protection 0 1 Program 2 0 Program mode cleared Transition to program mode Setting condition When FWE 1 and SWE 1 and ESU2 1 1 Erase 2 0 Erase mode cleared Transition to erase m...

Page 1043: ...lock Select Register 2 EBR2 FLASH ROM H8S 2194 FLASH Version Only 7 EB7 0 R W 6 EB6 0 R W 5 EB5 0 R W 4 EB4 0 R W 3 EB3 0 R W 0 EB0 0 R W 2 EB2 0 R W 1 EB1 0 R W Bit EBR2 Initial value R W Division of...

Page 1044: ...1k bytes EB1 1k bytes EB2 1k bytes EB3 1k bytes EB4 28k bytes EB5 16k bytes EB6 8k bytes EB7 8k bytes EB8 32k bytes EB9 32k bytes EB10 32k bytes EB11 32k bytes EB12 32k bytes EB13 32k bytes Address H...

Page 1045: ...are shown in table C 1 Legend OUT G IN OUT G IN PMOS NMOS Clocked gate signal transmitted when G 1 Signal transmitted when G 0 Symbols RD Read signal RST Reset signal LPM Power down mode signal 1 in...

Page 1046: ...leep Mode P00 AN0 to P07 AN7 PMR0n RD SCH3 to SCH0 Hi Z Retained Hi Z AN8 to ANB HCH1 HCH0 Hi Z Retained Hi Z Retained Pull up MOS OFF Subactive mode Functions Other modes Hi Z P10 54 to P15 54 P16 PU...

Page 1047: ...7 PCR17 TMOW PDR17 PMR17 PCR17 RD Hi Z Retained Pull up MOS OFF Subactive mode Functions Other modes Hi Z Retained Pull up MOS OFF Subactive mode Functions Other modes Hi Z P20 SI1 PUR20 PCR20 RD PDR2...

Page 1048: ...ned Pull up MOS OFF Subactive mode Functions Other modes Hi Z Retained Pull up MOS OFF Subactive mode Functions Other modes Hi Z P22 SCK1 PUR22 PCR22 SCKO SCKI PDR22 CKOE PCR22 RD CKIE SCKO SCKI CKOE...

Page 1049: ...Than Sleep Mode P23 SDA P24 SCL PUR2n PCR2n SDA SCL PDR2n IICE PCR2n RD IICE IICE SDA SCL IICE I2 C bus enable signal n 3 4 Hi Z Retained Pull up MOS OFF Subactive mode Functions Other modes Hi Z P26...

Page 1050: ...PDR25 PMR25 PCR25 SI2 PMR25 Hi Z When SI2 input is selected pin input should be fixed high or low Retained Pull up MOS OFF Subactive mode Functions Other modes Hi Z P27 SCK2 PUR27 PCR27 SCKO PDR27 PMR...

Page 1051: ...Z When 6 input is selected pin input should be fixed high or low P31 STRB P32 PWM0 P33 PWM1 P34 PWM2 P35 PWM3 P36 BUZZ P37 TMO PUR3n PCR3n OUT PDR3n PMR3n PCR3n n 1 to 7 RD OUR P31 STRB SC12 strobe o...

Page 1052: ...modes Hi Z P41 FTIA P42 PTIB P43 FTIC P44 FTID RD PDR4n PCR4n IN FTIA FTIB FTIC FTID n 1 to 4 IN Hi Z Note As pins FTIA to FTID are always active except in the standby and watch modes a high or low le...

Page 1053: ...R47 PCR47 Hi Z Retained Subactive mode Functions Other modes Hi Z Retained Subactive mode Functions Other modes Hi Z P50 75 RD PDR50 TRGE PCR50 ADTRG TRGE A D trigger input control signal TRGE Hi Z Wh...

Page 1054: ...des Hi Z P52 TMBI P53 TRIG RD PDR5n PMR5n PCR5n IN IN TMBI TRIG n 2 3 PMR5n Hi Z When TMBI and TRIG input are selected pin input should be fixed high or low P60 RP0 to P67 RP7 RD n 0 to 7 PDRS6n PCRS6...

Page 1055: ...RD PDR8n PMR8n PCR8n IN IN EXTTRG EXCAP n 0 1 PMR8n Hi Z When EXTTRG and EXCAP input are selected pin input should be fixed high or low P82 SV1 P83 SV2 OUT PDR8n PMR8n PCR8n RD OUT SV1 SV2 n 2 3 Hi Z...

Page 1056: ...nput is selected pin input should be fixed high or low AUDIOFF VIDEOFF OUT LPM LPM power down mode signal Hi Z Hi Z Hi Z CAPPWM DRMPWM Low output Low output Low output Vpulse LPM Three level control c...

Page 1057: ...han Sleep Mode C Rotary PS0 H Ampsw PS1 OUT SPDRn SPMRn SPCRn RD OUT C Rotary H Ampsw n 0 1 Hi Z Hi Z Hi Z Hi Z Hi Z EXCTL PS4 RD SPDR4 SPMR4 SPCR4 EXCTL SPMR4 Hi Z When EXCTL input is selected pin in...

Page 1058: ...LREF CTLBias CTLFB CTLAmp O CTLSMT i CTLGR3 to 1 CTLFB CTLGR0 AMPSHORT REC CTL AMPON PB CTL PB CTL PB CTL CTLSMT i CTLAmp o CTLFB CTLREF CTL CTL CTLBias Note Note Be sure to set a capacitor between CT...

Page 1059: ...unctions Retained High imped ance High imped ance Functions Retained P37 to P30 High imped ance Functions Retained High imped ance High imped ance Functions Retained P47 to P40 High imped ance Functio...

Page 1060: ...ot exceed the respective power supply voltage VCC AVCC VCC AVCC SVCC Vin Microcomputer section power supply voltage A D converter power supply voltage Servo section power supply voltage Pin applied vo...

Page 1061: ...pins should be handled when the switching circuit for four head special effects playback is not used COMP is an input pin and the other two are output pins When the switching circuit for four head sp...

Page 1062: ...ure E 3 R1 DRMPWM CAPPWN C1 Figure E 3 Sample External Circuit for Servo Section 2 Sync Signal Detection Circuit Section Figure E 4 shows an example of the external circuit for the sync signal detecti...

Page 1063: ...H8S 2193 Mask ROM version HD6432193 HD6432193 F 112 pin QFP FP 112 H8S 2192 Mask ROM version HD6432192 HD6432192 F 112 pin QFP FP 112 H8S 2194 Series H8S 2191 Mask ROM version HD6432191 HD6432191 F 11...

Page 1064: ...Unit mm Dimension including the plating thickness Base material dimension 0 10 23 2 0 3 0 32 0 08 0 65 1 6 0 8 0 3 0 17 0 05 3 05 Max 23 2 0 3 84 57 56 29 112 1 28 20 85 2 70 0 8 0 13 M 0 10 0 15 0 10...

Page 1065: ...Date 1st Edition November 1998 2nd Edition November 2000 Published by Electronic Devices Sales Marketing Group Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hi...

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Summary of Contents for Hitachi H8S/2191

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Renesas Hitachi H8S/2191, Hardware Manual, Page: 156 / 1065

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Summary of Contents for Hitachi H8S/2191

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