Renesas Hitachi H8S/2191, Hardware Manual

Page: 837 / 1065

Rev. 2.0, 11/00, page 810 of 1037
28.16 Servo Interrupt
28.16.1 Overview
The interrupt exception processing of the servo module is started by one of ten factors, i.e. the
drum speed error detector (
×
2), drum phase error detector, capstan speed error detector (
×
2),
capstan phase error detector, HSW timing generator (
×
2), sync detector and CTL circuit. For
these interrupt factors, see each of their circuit sections in this manual.
Also, see section 5, Exception Handling.
28.16.2 Register Configuration
Table 28.27 shows the list of the registers which control the interrupt of the servo section.
Table 28.27 Registers which Control the Interrupt of the Servo Section
Name Abbrev. R/W Size Initial Value Address
Servo interrupt
permission register 1 SIENR1 R/W Byte H'00 H'FD0B8
Servo interrupt
permission register 2 SIENR2 R/W Byte H'FC H'FD0B9
Servo interrupt request
register 1 SIRQR1 R/W Byte H'00 H'FD0BA
Servo interrupt request
register 2 SIRQR2 R/W Byte H'FC H'FD0BB
28.16.3 Register Description
(1) Servo Interrupt Permission Register 1 (SIENR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5 6
0
7
IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
0
R/W
IEDRM3
R/W R/W R/W
IEDRM2 IEDRM1
Bit :
Initial value :
R/W :
SIENR1 controls the permission and prohibition of the interrupt of the servo section. SIENR1 is
an 8-bit readable/writable register. It is initialized to H'00 by a reset, stand-by or module stop.