Renesas Hitachi H8S/2191, Hardware Manual

Page: 139 / 1065

Rev. 2.0, 11/00, page 112 of 1037
(1) Interrupt Acceptance Control and 3-Level Control
In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is
performed by means of the I and UI bits in CCR, and ICR (control level).
Table 6.6 shows the interrupts selected in each interrupt control mode.
Table 6.6 Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bit Interrupt
Control
Mode
I UI Selected Interrupts
0
*
All interrupts (control level 1 has priority) 0
1
*
NMI and address trap interrupts
0 * All interrupts (control level 1 has priority)
0 NMI, address trap and control level 1 interrupts
1
1
1 NMI and address trap interrupts
Note:
*
Don't care
(2) Default Priority Determination
The priority is determined for the selected interrupt, and a vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected
and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 6.7 shows operations and control signal functions in each interrupt control mode.
Table 6.7 Operations and Control Signal Functions in Each Interrupt Control Mode
Setting
Interrupt Acceptance Control,
3-Level Control
Interrupt
Control
Mode
INTM1 INTM0 I UI ICR
Default Priority
Determination
0 0
{
IM

PR
{
1
0
1
{
IM IM PR
{
Legend:
{
: Interrupt operation control performed
IM: Used as interrupt mask bit
PR: Sets priority

: Not used