Renesas Hitachi H8S/2191, Hardware Manual

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Rev. 2.0, 11/00, page 196 of 1037
program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after the
elapse of (y)
µ
s or more, the operating mode is switched to program mode by setting the Pn bit
in FLMCRn. The time during which the Pn bit is set is the flash memory programming time.
Make a program setting so that the time for one programming operation is within the range of
(z)
µ
s.
8.5.2 Program-Verify Mode (n =1 for addresses H'00000 to H'1FFFF and n = 2 for
addresses H'20000 to H'3FFFF)
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the Pn bit in
FLMCRn is cleared, then the PSUn bit in FLMCRn is cleared at least (
α
)
µ
s later). The
watchdog timer is cleared after the elapse of (
β
)
µ
s or more, and the operating mode is switched
to program-verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify
mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy
write should be executed after the elapse of (
γ
)
µ
s or more. When the flash memory is read in
this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least
(
ε
)
µ
s after the dummy write before performing this read operation. Next, the originally written
data is compared with the verify data, and reprogram data is computed (see figure 8.12) and
transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-
verify mode, wait for at least (
η
)
µ
s, then clear the SWE bit in FLMCR1. If reprogramming is
necessary, set program mode again, and repeat the program/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times
on the same bits.