Renesas Hitachi H8S/2191, Hardware Manual, Page: 1000 / 1065

Rev. 2.0, 11/00, page 973 of 1037
H'D12D: Prescaler Unit Control/Status Register PCSR: PSU
0
0
1
0
R/W
2
0
R/W
3
1
4
0
R/W
5
0
6
0
7
R/W R/W
ICEG
R/W
ICIE
0
R/(W)
*
ICIF NCon/off DCS2 DCS1 DCS0
Note: * Only 0 can be written to clear the flag.
Interrupt request by input capture is disabled
Interrupt request by input capture is enabled
0
1
Input capture interrupt enable bit
Frequency division clock output select bits
Frequency division
clodk output select
0 0 0 PSS, output
φ
/32
DCS1 DCS0 DCS2
1 PSS, output
φ
/16
1 0 PSS, output
φ
/8
1 PSS, output
φ
/4
0 1 0 PSW, output
φ
W/32
1 PSW, output
φ
W/16
1 0 PSW, output
φ
W/8
1 PSW, output
φ
W/4
Input capture interrupt flag
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When input capture is executed at IC pin edge
0
1
Noise cancel function of IC pin is disabled
Noise cancel function of IC pin is enabled
0
1
Noise cancel ON/OFF bit
IC pin edge select bit
Falling edge of IC pin input is detected
Rising edge of IC pin input is detected
0
1
Bit :
Initial value :
R/W :
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