Renesas Hitachi H8S/2191, Hardware Manual, Page: 761 / 1065

Rev. 2.0, 11/00, page 734 of 1037
(7) Digital Filter Control Register (DFUCR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6 7
— —
— — R/W R/W R/W
PTON CP/DP CFEPS DFEPS CFESS DFESS
1 1
Bit :
Initial value :
R/W :
DFUCR is an 8-bit readable/writable register which controls the operation of the digital filter. It
accepts a byte-access only. If it was word-accessed, operation is not assured.
Bits 7 and 6 are reserved. No write in them is valid. It is initialized to H'00 by a reset, stand-by
or module stop.
Bits 7 and 6: Reserved
No read or write is valid. If a read is attempted, an undefined value is read out.
Bit 5: Phase System Computation Result PWM Output Bit (PTON)
Outputs the computation results of only the phase system to PWM. (The computation results of
the drum phase system is output to the CAPPWM pin, and that of the capstan phase system is
output to the DRMPWM pin.)
Bit 5
PTON Description
0 Outputs the results of ordinary computation of the filter to PWM pin (Initial value)
1 Outputs the computation results of only the phase system to PWM pin
Bit 4: PWM Output Selection Bit (CP/
'3 '3)
Selects whether the phase system computation results when PTON was set to 1 is output to the
drum or capstan. The PWM of the selected side outputs ordinary filter computation results
(speed system of MIX).
Bit 4
CP/
'3
'3
Description
0 Outputs the drum phase system computation results (CAPPWM) (Initial value)
1 Outputs the capstan phase system computation results (DRMPWM)