Renesas Hitachi H8S/2191, Hardware Manual, Page: 325 / 1065

Rev. 2.0, 11/00, page 298 of 1037
Bit 5: Enabling Interrupt of the Timer B (TMBIE)
This bit works to permit/prohibit occurrence of interrupt of the Timer B when the TCB
overflows and when the TMBIF is set to 1.
Bit 5
TMBIE Description
0 Prohibits occurrence of interrupt of the Timer B (Initial value)
1 Permits occurrence of interrupt of the Timer B
Bits 4 to 3: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Bits 2 to 0: Clock Selection (TMB12 to TMB10)
These bits work to select the clock to input to the TCB. Selection of the rising edge or the
falling edge is workable with the external event inputs.
Bit 2 Bit 1 Bit 0
TMB12 TMB11 TMB10 Descriptions
0 0 0 Internal clock: Counts at
φ
/16384 (Initial value)
0 0 1 Internal clock: Counts at
φ
/4096
0 1 0 Internal clock: Counts at
φ
/1024
0 1 1 Internal clock: Counts at
φ
/512
1 0 0 Internal clock: Counts at
φ
/128
1 0 1 Internal clock: Counts at
φ
/32
1 1 0 Internal clock: Counts at
φ
/8
1 1 1 Counts at the rising edge and the falling edge of external
event inputs (TMBI)
*
Note: * The edge selection for the external event inputs is made by setting the PMR51 of the
port mode register 5 (PMR5). See section 13.2.4, Port Mode Register 5 (PMR5).