Renesas Hitachi H8S/2191, Hardware Manual

Page: 1018 / 1065

Rev. 2.0, 11/00, page 991 of 1037
H'D15F: Slave Address Register SAR: IIC Bus Interface
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Format select bit
SAR SARX Format select
Bit 0 Bit 0
FS FX
0 0 I
2
C bus format
• SAR and SARX slave addresses recognized
1 I
2
C bus format
• SAR slave address recognized
• SARX slave address ignored
1 0 I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
1 I
2
C bus format
• SAR and SARX slave addresses ignored
Bit :
Initial value :
R/W :
H'FFB0: Trap Address Register 0 TAR0: ATC
H'FFB3: Trap Address Register 1 TAR1: ATC
H'FFB6: Trap Address Register 2 TAR2: ATC
0
0
1
0
R/W
2
0
R/W
3 4 5 6 7
R/W
A18 A17 A16
0 0
R/W
0
R/W R/W
A23 A22 A21
0 0
R/W R/W
A20 A19
0
0
1
0
R/W
2
0
R/W
3 4 5 6 7
R/W
A10 A9 A8
0 0
R/W
0
R/W R/W
A15 A14 A13
0 0
R/W R/W
A12 A11
0 1
0
R/W
2
0
R/W
3 4 5 6 7
A2 A1
0 0
R/W
0
R/W R/W
A7 A6 A5
0 0
R/W R/W
A4 A3
0
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
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