Renesas Hitachi H8S/2191, Hardware Manual

Page: 257 / 1065

Rev. 2.0, 11/00, page 230 of 1037
Table 10.4 External Clock Output Settling Delay Time
(Conditions: V
CC
= 4.0 V to 5.5 V, AV
CC
= 4.0 V to 5.5 V, V
SS
= AV
SS
= 0 V)
Item Symbol Min Max Unit Notes
External clock output settling
delay time t
DEXT
*
500
 µ
s Figure 10.7
Note:
*
t
DEXT
includes 20 t
CYC
of
5(6
pulse width (t
RESW
).
t
DEXT
*
RES
(Internal)
OSC1
V
CC
4.0 V
Note: * t
DEXT
includes 20 t
cyc
of RES pulse width (t
RESW
).
Figure 10.7 External Clock Output Settling Delay Timing