Renesas Hitachi H8S/2191, Hardware Manual

Page: 30 / 1065

Rev. 2.0, 11/00, page 3 of 1037
Item Specifications
Timer
(4) Timer L
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8-bit up/down counter
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Clock source can be selected among 2 types of internal clock, CFG
frequency division signal, and PB and REC-CTL (control pulse)
•
Compare-match clearing function/auto reload function
(5) Timer R
•
Three reload timers
•
Mode discrimination
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Reel control
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Capstan motor acceleration/deceleration detection function
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Slow tracking mono-multi
(6) Timer X1
•
16-bit free-running counter
•
Clock source can be selected among 3 types of internal clock and DVCFG
•
Two output compare outputs
•
Four input capture inputs
(7) Watchdog timer
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Functions as watchdog timer or 8-bit interval timer
•
Generates reset signal or NMI at overflow
Prescaler unit
•
Divides system clock frequency and generates frequency division clock
for supporting module functions
•
Divides subclock frequency and generates input clock for Timer A (clock
time base)
•
Generates 8-bit PWM frequency and duty period
•
8-bit input capture at external signal edge
•
Frequency division clock output enabled
PWM ■
Three types of PWM are incorporated
(1) 14-bit PWM: Pulse resolution type x 1 channel
(2) 8-bit PWM: Duty control type x 4 channels
(3) 12-bit PWM: Pulse pitch control type x 2 channels