Renesas Hitachi H8S/2191, Hardware Manual

Page: 922 / 1065

Rev. 2.0, 11/00, page 895 of 1037
Instruction
Fetch
Branch
Address
Read
Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic
I J K L M N
SUBX SUBX #xx:8,Rd
SUBX Rs,Rd 1
1
TAS TAS @ERd
*
3
2 2
TRAPA TRAPA #x:2 2 2 2/3
*
1
2
XOR XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd 1
1
2
1
3
2
XORC XORC #xx:8,CCR
XORC #xx:8,EXR 1
2
Notes: 1. 3 applies when EXR is valid, and 2 applies when invalid.
2. Applies when the transfer data is n bytes.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.