Renesas Hitachi H8S/2191, Hardware Manual

Page: 815 / 1065

Rev. 2.0, 11/00, page 788 of 1037
•
CFG frequency division register 1 (CDIVR1)
0
0
1
0
W
2
0
W
3 4
0
W
5
0
6 7
—
—
W W
CDV15 CDV14
0
W
CDV16
0
W
CDV13 CDV12 CDV11 CDV10
1
Bit :
Initial value :
R/W :
The CFG frequency division register 1 (CDIVR1) is an 8-bit write-only register to set the
CFG division value (N-1 for N division). If a read is attempted, an undetermined value is
read out. Bit 7 is reserved.
The frequency division value is written in the reload register and the down counter at the
same time.
CFG's frequency is divided by N at its rising edge or both edges. If the register value was
0, no division operation is performed, and the DVCFG signal with the same input cycle
with the CFG signal is output. The DVCFG signal is sent to the capstan speed error
detector. It is initialized to H'80 by a reset or stand-by together with the capstan
frequency division register and the down counter.
•
CFG frequency division register 2 (CDIVR2)
0
0
1
0
W
2
0
W
3 4
0
W
5
0
6 7
—
— W W
CDV25 CDV24
0
W
CDV26
0
W
CDV23 CDV22 CDV21 CDV20
1
Bit :
Initial value :
R/W :
The CFG frequency division register 2 (CDIVR2) is an 8-bit write-only register to set the
CFG division value (N-1 for N division). If a read is attempted, an undetermined value is
read out. Bit 7 is reserved.
The frequency division value is written in the reload register and the down counter at the
same time.
CFG's frequency is divided by N at its rising edge or both edges. If the register value was
0, no division operation is performed, and the DVCFG signal with the same input cycle
with the CFG signal is output. The DVCFG2 signal is sent to the capstan speed error
detector and the Timer L.
The DVCFG2 circuit has no mask timer function.
The frequency division counter for the DVCFG2 signal starts its division operation at the
point data was written in CDIVR2. If synchronization is required for phase matching, for
example, do it by writing in CDIVR2. If the DVTRG bit of the CDVC register was 0, the
register synchronizes with the switching timing from PB (ASM) to REC.
It is initialized to H'80 by a reset or stand-by together with the capstan frequency division
register and the down counter.